clock divider

一个clock的产生：

1) Clock source的选择：

cgm_mux5(.clk_out,

                 .clk_in0,

                 .clk_in1,

                 .clk_in2,

                 .clk_in3,

                 .clk_in4,

                 .sel_in,

                 .ptest_scan_dc_mode  );

在dc_scan mode下，选择某一个clock freq。

Sel_in_scan = {3{~ptest_scan_dc_mode}} & sel_in[2:0]

将所有的mux做成2x1的。5选1的mux，可以先进行4x1的选择，再进行2x1的选择，4选1的mux，可以分为三个2x1的选择。

Z_i0 = S0  ?  I1 : I0;

Z_i1 = S0  ?  I3 : I2;

Z   = S1  ? Z_I1 : Z_I0;

2)       Clock div的处理：

u_cgm_divn_clk_sim0(

                      .clk_div  (clk_sim0_gen),

                      .div_ratio  (cgm_ratio_sim0),

                      .cgm_busy  (cgm_busy_sim0),

                      .clk_in  (clk_sim0_mux),

                      .rst_clk_in  (rst_clk_n),

                      .cgm_div  (cgm_sim0_div_ac[2:0]),

                      .cgm_en  (cgm_sim0_en_ac),

                      .ptest_scan_dc_mode  (ptest_scan_dc_mode),

                      .ptest_icg_mode  (ptest_icg_mode),

                      .clk_scan  (clk_scan_occ), );

首先在clk_in与clk_scan之间进行mux，产生clock，clk_in_scan(该clk只用在cgm_en的同步)。

再次基于clk_in_scan进行cgm_en的sync处理。这时的rst可能并没有进行同步释放处理。

再次cgm_active = cgm_en_sync | ～cnt_zero。(cnt_zero无效时，clock为低电平允许进行gate操作)

再次加入clock_gate

clk_gate u_clk_gate_in(

                     .genp (cgm_active),

                     .lclkp (clk_In)，

                     .testmodep (ptest_icg_mode),

                     .gclkp (clk_in_gate));

再次加入mux，在clk_scan和clk_in_gate之间进行选择。Selcet信号ptest_scan_dc_mode，产生clk_in_gate_scan

再次进行Counter Divider

Always @(posedge clk_in_gate_scan or negedge rst_clk_n)

      If(~rst_clk_n)    div_cnt < = WIDTH{1’b0}

         else if(cnt_zero)  div_cnt <= cgm_div[WIDTH-1:0]

         else div_cnt <= div_cnt[WIDTH-1:0] – 1’b1;

再次cnt_zero和cnt_half的组合逻辑。

assign cnt_zero = (div_cnt[WIDTH:0] == {WIDTH{1’h0}} ) ？ 1’b1 : 1’b0;

assign cnt_half = (div_cnt[WIDTH-1:0] == (cgm_div[WIDTH-1:1] + cgm_div[0])) ? 1’b1 : 1’b0;

再次generated clock

Always @(posedge clk_in_gate or negedge rst_clk_n)

      If(~rst_clk_n)  clk_div_gen = 1’b0;

      else if(div_sel == 1’b0)  clk_div_gen = 1’b0;

      else if(cnt_zero) clk_div_gen = 1’b1;

      else if(cnt_half) clk_div_gen = 1’b0;

      else clk_div_gen = clk_div_gen;

3) 最终mux选择。

Assign div_sel = (cgm_div[WIDTH-1:0] == {WIDTH{1’b0}}) ? 1’b0 : 1’b1;

Assign div_sel_scan = ~ptest_scan_dc_mode & div_sel;

Mux2x1 u_mux2_clk_div(

                       .in1  (clk_in_gate),

                       .in2  (clk_div_gen),

                       .c  (div_sel_scan),

                       .out  (clk_div)

);

Assign div_ratio = cgm_active & cnt_zero;

Assign cgm_busy = cgm_en | cgm_en_sync | ~cnt_zero