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  • Prime Time使用

    PrimeTime一般用作sign off的timing check,也可用在DC之后的netlist的timing analysis

    一般的使用流程:

    1) Read design data,--------------netlist,db,sdf,parasitics,milkway

    2) Constrain design,--------------sdc

    3) Specify env and analysis condition,

    4) Check design and analysis setup,

    5) Perform a full analysis,

    Read design:

    通过set  search_path ""  来设置db/lib

          set  link_path ""   (optional)

          link_design  TOP   (指定design top)

        

    read_verilog/read_vhdl 来读入netlist到PrimeTime

    read_parasitics/read_sdf 进行annotation

    read_sdc/source  进行timing constraints和exception约束

    Constraining The Design:

    约束clock characteristics

    约束input delay at input port

    约束output delay at output port

    针对clock,create_clock创建,include name,source,period,waveform

                    clock network,set_clock_uncertainty, set_propagated_clock, set_clock_transiaction, set_clock_latency 

                    create_generated_clock

    set_input_delay

    set_output_delay

    Specify env and analysis condition

    Specify process, temperature, voltage

    apply case analysis and mode analysis             set_case_analysis single/BC_WC/OCV    set_case_analysis/set_mode(lib中不同的characteristic)

    specify driving cell at input ports, load at output ports          set_driving_cell   set_load

    specify timing exceptions           set_min_delay    set_max_delay    set_disable_timing

    specify wire load model and back-annotated           set_wire_load_model/read_sdf/read_parastics

    Check Design and analysis setup

    check timing

    report_design

    report_port

    report_net

    report_lib

    report_path_group

    report_clock

    report_wire_load

    Performing a Full Analysis

    report_timing   -delay_type/-from/-to/-through/-rise_through/-rise_from

    report_constraint

    report_analysis_coverage

    report_delay_calculation

    PrimeTime中的Design Objects,可以使用get命令,  set_input_delay 2.3 [get_ports IN*]

    cell---------instance in the design, include reference hierarchical blocks and library cell

    lib_cell--------cells in technology library

    lib_pin-------pins in library cells

    net----------nets in current design

    pin-----pins of lower-level cells in the design, can be input/ output/ inout

    port-------ports of current design, can be input/ output/ inout

    path group----Timing reports organized by path group

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  • 原文地址:https://www.cnblogs.com/-9-8/p/6023119.html
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