c++:
__asm
{
push eax
push ebx
push ecx
push edx
xor eax,eax
cpuid
...
pop edx
pop ecx
pop ebx
pop eax
}
CPUID指令所支持的最大值和厂家的名称字符串参数
EAX = 00000000h
mov eax,0 或者xor eax,eax
输出
EAX=xxxx_xxxxh
得到CPUID指令所支持的最大值 EBX-EDX-ECX 厂家的名称字符串处理器
type/family/model/stepping和面貌标识参数
EAX = 00000001h
mov eax ,1
输出
EAX=xxxx_xxxxh
处理器type/family/model/stepping
extended family 是 bits 27..20.
extended model 是 bits 19..16
type是 bit 13 和 bit 12
family是bits 11..8.
如果是Intel的cpu并且为F需要看extended family
model 是 bits 7..4.
如果是Intel的cpu并且为F需要看extended model
stepping 在 bits 3..0
Stepping描述的是处理器的细节.
EBX=aall_ccbbh
brand ID是 bit 7..0.
CLFLUSH CLFLUSH (8-byte)在 bits 15..8.
CPU count 逻辑处理器数量 bits 23..16.
APIC ID 默认（固定的）APIC ID是bits 31..24.
ECX=xxxx_xxxxh feature flags
EDX=xxxx_xxxxh feature flags
备注：
尽管Intel P6 处理器不支持 SEP,在这里仍然会虚报（真不知Intel是怎么想的）
早期AMD K5处理器 (SSA5)会假报支持 PGE.
处理器配置描述参数
EAX = 00000002h
mov eax ,2
输出
EAX.15..8
EAX.23..16
EAX.31..24
EBX.0..7
EBX.15..8
EBX.23..16
EBX.31..24
ECX.0..7
ECX.15..8
ECX.23..16
ECX.31..24
EDX.0..7
EDX.15..8
EDX.23..16
EDX.31..24
相对应的代表结果：
00h null descriptor (=unused descriptor)
01h code TLB, 4K pages, 4 ways, 32 entries
02h code TLB, 4M pages, fully, 2 entries
03h data TLB, 4K pages, 4 ways, 64 entries
04h data TLB, 4M pages, 4 ways, 8 entries
06h code L1 cache, 8 KB, 4 ways, 32 byte lines
08h code L1 cache, 16 KB, 4 ways, 32 byte lines
0Ah data L1 cache, 8 KB, 2 ways, 32 byte lines
0Ch data L1 cache, 16 KB, 4 ways, 32 byte lines
10h data L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
15h code L1 cache, 16 KB, 4 ways, 32 byte lines (IA-64)
1Ah code and data L2 cache, 96 KB, 6 ways, 64 byte lines (IA-64)
22h code and data L3 cache, 512 KB, 4 ways (!), 64 byte lines, dual-sectored
23h code and data L3 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored
25h code and data L3 cache, 2048 KB, 8 ways, 64 byte lines, dual-sectored
29h code and data L3 cache, 4096 KB, 8 ways, 64 byte lines, dual-sectored
39h code and data L2 cache, 128 KB, 4 ways, 64 byte lines, sectored
3Bh code and data L2 cache, 128 KB, 2 ways, 64 byte lines, sectored
3Ch code and data L2 cache, 256 KB, 4 ways, 64 byte lines, sectored
40h no integrated L2 cache (P6 core) or L3 cache (P4 core)
41h code and data L2 cache, 128 KB, 4 ways, 32 byte lines
42h code and data L2 cache, 256 KB, 4 ways, 32 byte lines
43h code and data L2 cache, 512 KB, 4 ways, 32 byte lines
44h code and data L2 cache, 1024 KB, 4 ways, 32 byte lines
45h code and data L2 cache, 2048 KB, 4 ways, 32 byte lines
50h code TLB, 4K/4M/2M pages, fully, 64 entries
51h code TLB, 4K/4M/2M pages, fully, 128 entries
52h code TLB, 4K/4M/2M pages, fully, 256 entries
5Bh data TLB, 4K/4M pages, fully, 64 entries
5Ch data TLB, 4K/4M pages, fully, 128 entries
5Dh data TLB, 4K/4M pages, fully, 256 entries
66h data L1 cache, 8 KB, 4 ways, 64 byte lines, sectored
67h data L1 cache, 16 KB, 4 ways, 64 byte lines, sectored
68h data L1 cache, 32 KB, 4 ways, 64 byte lines, sectored
70h trace L1 cache, 12 KμOPs, 8 ways
71h trace L1 cache, 16 KμOPs, 8 ways
72h trace L1 cache, 32 KμOPs, 8 ways
77h code L1 cache, 16 KB, 4 ways, 64 byte lines, sectored (IA-64)
79h code and data L2 cache, 128 KB, 8 ways, 64 byte lines, dual-sectored
7Ah code and data L2 cache, 256 KB, 8 ways, 64 byte lines, dual-sectored
7Bh code and data L2 cache, 512 KB, 8 ways, 64 byte lines, dual-sectore
7Ch code and data L2 cache, 1024 KB, 8 ways, 64 byte lines, dual-sectored
7Eh code and data L2 cache, 256 KB, 8 ways, 128 byte lines, sect. (IA-64)
81h code and data L2 cache, 128 KB, 8 ways, 32 byte lines
82h code and data L2 cache, 256 KB, 8 ways, 32 byte lines
83h code and data L2 cache, 512 KB, 8 ways, 32 byte lines
84h code and data L2 cache, 1024 KB, 8 ways, 32 byte lines
85h code and data L2 cache, 2048 KB, 8 ways, 32 byte lines
88h code and data L3 cache, 2048 KB, 4 ways, 64 byte lines (IA-64)
89h code and data L3 cache, 4096 KB, 4 ways, 64 byte lines (IA-64)
8Ah code and data L3 cache, 8192 KB, 4 ways, 64 byte lines (IA-64)
8Dh code and data L3 cache, 3096 KB, 12 ways, 128 byte lines (IA-64)
90h code TLB, 4K...256M pages, fully, 64 entries (IA-64)
96h data L1 TLB, 4K...256M pages, fully, 32 entries (IA-64)
9Bh data L2 TLB, 4K...256M pages, fully, 96 entries (IA-64)
处理器序列号
参数
EAX = 00000003h
mov eax ,3
输出
EBX=xxxx_xxxxh 处理器序列号(只只是Transmeta Crusoe)
ECX=xxxx_xxxxh 处理器序列号
EDX=xxxx_xxxxh 处理器序列号
备注
仅当PSN有效时. 才可以返回处理器序号，否则不支持该命令
扩展指令：所支持的最大值和厂商名称
参数
EAX＝ 80000000h
MOV EAX, 80000000h
输出
EAX=xxxx_xxxxh 最大值
EBX-EDX-ECX 厂家的名称字符串
扩展指令：处理器 family/model/stepping and features flags
参数
EAX=8000_0001h
mov eax, 80000001h
输出
EAX=0000_0xxxh 处理器 family/model/stepping
Family bits 11..8
Model bits 7..4.
Stepping bits 3..0
EDX=xxxx_xxxxh feature flags description of indicated feature
bit 31 (3DNow!) 3DNow!
bit 30 (3DNow!+) extended 3DNow!
bit 29 (LM) AA-64, Long Mode（也就是AMD的X86-64指令集）
bit 28 保留
bits 27..25 保留
bit 24 (MMX+)
bit 24 (FXSR) Cyrix specific: extended MMX
AMD K7: FXSAVE/FXRSTOR, CR4.OSFXSR
bit 23 (MMX) MMX
bit 22 (MMX+) AMD specific: MMX-SSE and SSE-MEM bit
21 保留
bit 20 (NX) EFER.NXE, P?E.NX, #PF(1xxxx)
bit 19 (MP) MP-capable #3
bit 18 保留
bit 17 (PSE36) 4 MB PDE
bits 16..13, CR4.PSE
bit 16 (FCMOV)
bit 16 (PAT) FCMOVcc/F(U)COMI(P) (implies FPU=1) AMD K7: PAT MSR, PDE/PTE.PAT
bit 15 (CMOV) CMOVcc
bit 14 (MCA) MCG_*/MCn_* MSRs, CR4.MCE, #MC
bit 13 (PGE) PDE/PTE.G, CR4.PGE
bit 12 (MTRR) MTRR* MSRs
bit 11 (SEP) SYSCALL/SYSRET, EFER/STAR MSRs #1
bit 10 保留 #1
bit 9 (APIC) APIC #2
bit 8 (CX8) CMPXCHG8B
bit 7 (MCE) MCAR/MCTR MSRs, CR4.MCE, #MC
bit 6 (PAE) 64bit PDPTE/PDE/PTEs, CR4.PAE
bit 5 (MSR) MSRs, RDMSR/WRMSR
bit 4 (TSC) TSC, RDTSC, CR4.TSD (doesn’t imply MSR=1)
bit 3 (PSE) PDE.PS, PDE/PTE.res, CR4.PSE, #PF(1xxxb)
bit 2 (DE) CR4.DE, DR7.RW=10b, #UD on MOV from/to DR4/5
bit 1 (VME) CR4.VME/PVI, EFLAGS.VIP/VIF, TSS32.IRB
bit 0 (FPU) FPU
备注
#0 Intel 处理器不支持; 返回值EAX, EBX, ECX, 和 EDX都是0
#1 AMD K6 处理器, model 6, uses 使用第十位指示SEP
#2 如果APIC是无效的,那么APIC读到的是0
#3 AMD CPUID=0662h的K7 处理器如果是具有多处理器能力的版本可能也报告时0
扩展指令：处理器名称
参数
EAX = 80000002h
EAX = 80000003h
EAX = 80000004h
MOV EAX,80000002H
MOV EAX,80000003H
MOV EAX,80000004H
输入
EAX=80000002h 得到处理器名称的第一部分
EAX=80000003h 得到处理器名称的第二部分
EAX=80000004h 得到处理器名称的第三部分
输出
EAX-EBX-ECX-EDX
备注
返回值为字符数组，以0H结尾 Intel只有P4以上才支持 Centaur的WinChip是否支持决定于是否支持3D Now！
扩展指令：L1缓存容量和入口数量
参数
EAX = 80000005h
mov eax ,80000005h
输出
EAX 4/2 MB L1 入口信息
31..24 data TLB associativity (FFh=full)
23..16 data TLB entries
15..08 code TLB associativity (FFh=full)
07..00 code TLB entries
EBX 4 KB L1入口信息
31..24 data TLB associativity (FFh=full)
23..16 data TLB entries
15..08 code TLB associativity (FFh=full)
07..00 code TLB entries
ECX data L1 信息描述
31..24 data L1 cache size in KBs
23..16 data L1 cache associativity (FFh=full)
15..08 data L1 cache lines per tag
07..00 data L1 cache line size in bytes
EDX code L1信息描述
31..24 code L1 cache size in KBs
23..16 code L1 cache associativity (FFh=full)
15..08 code L1 cache lines per tag
07..00 code L1 cache line size in bytes
备注
Cyrix 处理器使用00000002h做类似的描述
扩展指令：L2缓存容量和入口数量
参数
EAX = 80000006h
mov eax ,80000006h
输出
EAX 4/2 MB L2 入口信息
31..28 data TLB associativity #2
27..16 data TLB entries
15..12 code TLB associativity #2
11..00 code TLB entries
EBX 4 KB L2入口信息
31..28 data TLB associativity #1
27..16 data TLB entries
15..12 code TLB associativity #1
11..00 code TLB entries
ECX data L1 信息描述
EDX code L1信息描述
31..28 data TLB associativity #1
27..16 data TLB entries
15..12 code TLB associativity #1
11..00 code TLB entries
ECX 统一 L2 cache 信息 #32
31..16 #4 unified L2 cache size in KBs #3
15..12 #4 unified L2 cache associativity #1
11..08 #4 unified L2 cache lines per tag
07..00 unified L2 cache line size in bytes
备注
#1 0000b=L2 off, 0001b=direct mapped, 0010b=2-way, 0100b=4-way, 0110b=8-way, 1000b=16-way, 1111b=full
#2 AMD K7 处理器 L2 cache 必须依赖于此信息.
#3 AMD CPUID=0630h 的K7 处理器(Duron) 具有 64 KB二级缓存，但是却报告只有1KB.
#4 VIA Cyrix III CPUID=0670..068Fh (C5B/C5C)的处理器错误报告bits 31..24, 23..16, and 15..8.
扩展指令：电源管理信息(EPM)
参数
EAX = 80000007h
mov eax , 80000007h
输出
EDX EPM flags
bits 31..3 保留
bit2 (VID) voltage ID control supported
bit1 (FID) frequency ID control supported
bit0 temperature sensing diode supported
扩展指令：地址大小信息参数
EAX = 80000008h
mov eax ,80000008h
输出
EAX 地址大小信息
bits 31..16 保留
bits 15..08 virtual address
bits 07..00 physical address bits
Transmeta专用指令：处理器信息
参数
EAX = 80860001h
EAX = 80860002h
mov eax , 80860001h
mov eax , 80860002h
输出
mov eax , 80860001h
cpuid时
EAX=00000xxxh 处理器信息
bits 11..8 family .
bits 7..4 model
bits 3..0 stepping
EBX=aabb_ccddh hardware revision (a.b-c.d), if 20000000h: see EAX=l 80860002h register EAX instead
ECX=xxxx_xxxxh nominal core clock frequency (MHz)
EDX=xxxx_xxxxh feature flags description of indicated feature
bits 31..4 reserved
bit 3 (LRTI) LongRun Table Interface
bit 2 (???) unknown
bit 1 (LR) LongRun
bit 0 (BAD) recovery CMS active (due to a failed upgrade)
mov eax , 80860001h
cpuid时
EAX xxxx_xxxxh reserved or hardware revision (xxxxxxxxh)
see EAX＝l 8086_0001h register
EBX for details EBX aabb_ccddh software revision, part 1/2 (a.b.c-d-x)
ECX xxxx_xxxxh software revision, part 2/2 (a.b.c-d-x)
Transmeta专用指令：信息字符串
参数
EAX = 80860003h
EAX = 80860004h
EAX = 80860005h
EAX = 80860006h
mov eax , 80860003h
mov eax , 80860004h
mov eax , 80860005h
mov eax , 80860006h
输出
EAX-EBX-ECX-EDX 信息字符串
#1 例如：Transmeta 20000805 23:30 official release 4.1.4
#2 以00h为结尾的字符串
Transmeta专用指令：当前处理器频率
参数
EAX = 80860007h
mov eax , 80860007h
输出
EAX xxxx_xxxxh 当前时钟频率 (MHz)
EBX xxxx_xxxxh 当前电压 (mV)
ECX xxxx_xxxxh 当前占用率(0..100%)
EDX xxxx_xxxxh 当前的延迟 (fs)
AMD K6神秘指令未知功能一
参数
EAX = 8FFFFFFEh
mov eax , 8FFFFFFEh
输出
EAX 00494544h DEI (according to one source: Divide Et Impera = Divide And Rule)
EBX 00000000h 保留
ECX 00000000h 保留
EDX 00000000h 保留
AMD K6神秘指令未知功能二
参数
EAX = 8FFFFFFFh
mov eax , 8FFFFFFFh
输出
EAX-EBX-ECX-EDX
CString:NexGenerationAMD
其他指令
参数
EAX=xxxxxxxxh 其他
mov eax , xxxxxxxxh
输出
EAX=xxxx_xxxxh
EBX=xxxx_xxxxh
ECX=xxxx_xxxxh
EDX=xxxx_xxxxh
作用不明确