用VHDL设计多路选择器、锁存器和全加器

1.2选1多路选择器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21 IS
  PORT ( a,b : IN STD_LOGIC;
           s : IN STD_LOGIC;
           y : OUT STD_LOGIC );
END ENTITY mux21;
 
ARCHITECTURE one OF mux21 IS
  BEGIN
     y <= a WHEN s = '0' ELSE
          b WHEN s = '1';
END ARCHITECTURE one;

2.锁存器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity latch is
    Port ( d : in STD_LOGIC;
         ena : in STD_LOGIC;
           q : out STD_LOGIC
         );
end entity latch;

architecture one of latch is
 signal sig_save : STD_LOGIC;
 begin
   process (d,ena)
    begin
    
     if ena = '1' then
     sig_save <= d;
     end if ;
     
     q <= sig_save ;
   end process ;
end architecture one;

3.全加器

--或门逻辑描述
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

ENTITY or2 IS
  PORT (a,b :IN STD_LOGIC; c : OUT STD_LOGIC );
END ENTITY or2;
ARCHITECTURE fu1 OF or2 IS
  BEGIN
   c <= a OR b ;
END ARCHITECTURE fu1;

--半加器描述
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY h_adder IS
  PORT (a,b : IN STD_LOGIC; co,so : OUT STD_LOGIC);
END ENTITY h_adder;
ARCHITECTURE fh1 OF h_adder IS
 BEGIN
  so <= (a OR b)AND(a NAND b);--与非的作用：实现1+1=0
  co <= NOT( a NAND b);--与非：只有在1 NAND 1时返回0，其他情况返回1
END ARCHITECTURE fh1;

--全加器顶层设计描述

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY f_adder IS
  PORT ( ain,bin,cin : IN STD_LOGIC;
            cout,sum : OUT STD_LOGIC );
END ENTITY f_adder;

ARCHITECTURE fd1 OF f_adder IS
COMPONENT h_adder
 PORT ( a,b : IN STD_LOGIC;
      co,so : OUT STD_LOGIC);
 END COMPONENT;
 COMPONENT or2
   PORT (a,b : IN STD_LOGIC;
           c : OUT STD_LOGIC);
END COMPONENT;
SIGNAL d,e,f : STD_LOGIC;
 BEGIN
 u1 : h_adder PORT MAP( a =>ain,b =>bin,co=>d,so =>e);
 u2 : h_adder PORT MAP( a =>e,b =>cin,co =>f,so =>sum);
 u3 : or2 PORT MAP(a =>d,b =>f,c =>cout);
END ARCHITECTURE fd1 ;