/*******************************************************************************
********************** Configuration BOARD_BootClockRUN ***********************
******************************************************************************/
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!Configuration
name: BOARD_BootClockRUN
called_from_default_init: true
outputs:
- {id: AHB_clock.outFreq, value: 16 MHz}
- {id: APB_clock.outFreq, value: 16 MHz}
- {id: RTC_SLETimer_clock.outFreq, value: 32.768 kHz}
- {id: RTC_clock.outFreq, value: 16 MHz}
- {id: WDT_clock.outFreq, value: 16 MHz}
settings:
- {id: SYSCON.AUTO_M_MULT.scale, value: '6'}
- {id: SYSCON.CLK_32K_SEL.sel, value: SYSCON.XTAL32K}
- {id: SYSCON.CLK_SYS_SEL.sel, value: SYSCON.XTAL_DIV}
- {id: SYSCON.XTAL_DIV.scale, value: '2', locked: true}
sources:
- {id: SYSCON.XTAL.outFreq, value: 32 MHz, enabled: true}
- {id: SYSCON.XTAL32K.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
******************************************************************************/
void BOARD_BootClockRUN(void)
{
/* Power up/Power down the module. */
/* Set up clock selectors - Attach clocks to the peripheries 系统时钟树的选择*/
CLOCK_AttachClk(k32M_to_XTAL_CLK); /* Switch XTAL_CLK to 32M, 1: external crystal is 32 MHz，选择外部晶振32MHz*/
CLOCK_AttachClk(kXTAL32K_to_32K_CLK); /* Switch 32K_CLK to XTAL32K, 0: digital 32 kHz clock source is external 32 kHz crystal，选择外部晶振32.768kHz*/
CLOCK_AttachClk(kXTAL_to_SYS_CLK); /* Switch SYS_CLK to XTAL, 01: external 16/32 MHz crystal，系统时钟CLS_SYS选择外部晶振32MHz或16MHz*/
CLOCK_AttachClk(kAPB_to_WDT_CLK); /* Switch WDT_CLK to APB, 1: watchdog run at APB clock，看门狗时钟选择APB时钟*/
/* Set up dividers 设置分频*/
CLOCK_SetClkDiv(kCLOCK_DivOsc32mClk, 1U); /* Set OSC32M_DIV divider to value 2 = 16MHz 1: divides 32 MHz OSC clock into 16 MHz，32MHz分频16MHz*/
CLOCK_SetClkDiv(kCLOCK_DivXtalClk, 1U); /* Set XTAL_DIV divider to value 2, divide crystal clock when external crystal is 32 MHz, 1: the SYS_CLK is 16 MHz*/
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 0U); /* Set AHB_DIV divider to value 1, AHB_CLK: SYS_CLK / (AHB_DIV+1) AHP总线为16MHz/（0+1）= 16MHz*/
CLOCK_SetClkDiv(kCLOCK_DivFrg1, 0U); /* Set FRG_MULT1 to value 0, Set FRG_DIV1 to value 255 Flexcomm Clock Divider register*/
CLOCK_SetClkDiv(kCLOCK_DivFrg0, 0U); /* Set FRG_MULT0 to value 0, Set FRG_DIV0 to value 255 */
CLOCK_SetClkDiv(kCLOCK_DivApbClk, 0U); /* Set APB_DIV divider to value 1, APB总线=APB_CLK: AHB_CLK/(APB_DIV+1) = 16/（0+1）= 16MHz*/
/* Enable/Disable clock out source and pins.*/
/* Enable/Disable the specified peripheral clock.*/
}
以上就是NXP低功耗蓝牙集成芯片QN9080C的时钟配置案例，来自SDK，这里做了标注，就是RTC的时钟配置，代码中没有实现，只在开头处说是16MHz，以上是自己的学习记录，有错误的还请指出