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  • windows XP下 iverilog+GTKWave使用(三)

    windows XP下 iverilog+GTKWave使用(二)当中只有一些显示信息在终端里面,这里讲讲如何生成lxt2文件以便可以被GTKWave调用。在counter_tb.v文件里添加以下语句:

    initial
    		begin			
    			$dumpfile("test.vcd");
    			$dumpvars(0,test);
    		end

    最终文件如下:

    `timescale 1ns/1ns
    module test;
    
        /*Make a reset that pulses once.*/
    	reg reset = 0;
    	
    	initial
    		begin
    			#17 reset = 1;
    			#11 reset = 0;
    			#29 reset = 1;
    			#11 reset = 0;
    			#100 $stop;
    		end
    	
    	/*Make a regular pulsing closk*/
    	
    	reg clk = 0;
    	always #5 clk = !clk;
    	
    	wire [7:0] value;
    	counter c1 (value, clk, reset);
    	
    	initial
    		$monitor("At time %t, value = %h (%0d)",$time, value, value);
    	initial
    		begin			
    			$dumpfile("test.vcd");
    			$dumpvars(0,test);
    		end
    endmodule

    另存为counter_tb_gtk.v,然后进行下面的命令:
    G:\Verilog HDL\iverilog\Demo\counter>iverilog -o test counter.v counter_tb_gtk.v

    G:\Verilog HDL\iverilog\Demo\counter>ls
    counter.v     counter_tb_gtk.v  my_design  test
    counter_tb.v  file_list.f       mydesign

    G:\Verilog HDL\iverilog\Demo\counter>vvp -n test -lxt2
    LXT2 info: dumpfile test.vcd opened for output.
    At time                    0, value = xx (x)
    At time                   17, value = 00 (0)
    At time                   35, value = 01 (1)
    At time                   45, value = 02 (2)
    At time                   55, value = 03 (3)
    At time                   57, value = 00 (0)
    At time                   75, value = 01 (1)
    At time                   85, value = 02 (2)
    At time                   95, value = 03 (3)
    At time                  105, value = 04 (4)
    At time                  115, value = 05 (5)
    At time                  125, value = 06 (6)
    At time                  135, value = 07 (7)
    At time                  145, value = 08 (8)
    At time                  155, value = 09 (9)
    At time                  165, value = 0a (10)

    G:\Verilog HDL\iverilog\Demo\counter>cp test.vcd test.lxt

    G:\Verilog HDL\iverilog\Demo\counter>gtkwave test.lxt

    未完待续。。。(见(四))


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  • 原文地址:https://www.cnblogs.com/CodeWorkerLiMing/p/12007735.html
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