理解Σ-Δ调制
目录
Σ-Δ调制
一个Σ-Δ ADC通常由Σ-Δ调制器和之后的抽取滤波器组成。Σ-Δ调制是数据变换器领域中最高效的一种变换形式,在通信系统、专业音响和精密测量中都有应用。Σ-Δ调制的目的在于,通过传输连续采样点之间的值变化量(Δ)而不是采样值本身,来达到更高的传输效率。ADC和DAC都可以采用Σ-Δ调制。
过采样减轻了带内噪声的影响,这有利于Σ-Δ ADC的模拟部分的工作;而噪声成型将噪声移出信号频带;之后数字滤波将噪声从需求频带内去除,并最终抽取或降采样数据。在考虑调制器本身之前,有必要理解一些相关的重要概念:量化噪声、过采样和噪声成型。
量化噪声
一个ADC的量化信号可以被表述为输入信号和量化噪声之和:VQuantized = VIn + ε (1)
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Eq2.gif)
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Eq3.gif)
过采样
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Eq4.gif)
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Eq5.gif)
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_FIG1all.gif)
1.一个假想的Σ-Δ ADC中的信号分量频谱图包括一个在任意采样率fs(其中fs> 2fO,例如大于奈奎斯特频率)下的平均噪声基底(average noise floor)(a)。当采样率乘上一个因子k时,噪声功率被分散在一个更宽的频率范围上 (b)。
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Eq5.gif)
过采样对于噪声的影响
对输入过采样可以减少噪声,这个效应在 Σ-Δ调制器上还要更明显1。计算一个L阶M倍过采样率的调制器的噪声的通用公式如下:![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Eq7.gif)
噪声成型
通过过采样,噪声频谱被分散在一个更宽的范围。 Σ-Δ调制的下一步是成型噪声并将大多数的噪声频谱移到更高频上,因此带内噪声被显著降低,这个概念被称为噪声成型。(Fig. 2)。![2. To achieve noise shaping, the output signal, Y, is fed back and summed with the input signal, X. The result is then fed to an amplifier block with gain of 1/f, the output of which summed with the signal Q(n). 2. To achieve noise shaping, the output signal, Y, is fed back and summed with the input signal, X. The result is then fed to an amplifier block with gain of 1/f, the output of which summed with the signal Q(n).](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_FIG2.gif)
这个简单的反馈系统可表示如下:
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Eq8.gif)
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Eq9.gif)
![3. Following noise shaping, a digital filter removes most of the noise. Filtering can be performed in the digital or analog domain. In this case, the modulator is emitting a bit stream, so a digital filter is appropriate. Because the oversampling factor was k, noise is pushed out to higher frequencies. By filtering at fs/2, most of the noise will be out of band. 3. Following noise shaping, a digital filter removes most of the noise. Filtering can be performed in the digital or analog domain. In this case, the modulator is emitting a bit stream, so a digital filter is appropriate. Because the oversampling factor was k, noise is pushed out to higher frequencies. By filtering at fs/2, most of the noise will be out of band.](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808eesigmadelta_FIG3.gif)
3. 噪声成型之后,通过一个数字滤波器可以去除掉多数的噪声。滤波可以采用数字或模拟方式,在此情形下,调制器输出一串比特流,所以数字滤波较为适宜。因为过采样因子是k,噪声被移向更高频。通过在 fs/2处滤波,多数噪声将被移出频带。
调制器如何工作
一个一阶Σ-Δ调制器包括一个子DAC和由一个积分器,一个比较器组成的子ADC。子DAC通常简单地由一个在两个基准电压源之间切换的开关构成,锁存功能通常嵌入在比较器中。![4. In a typical first-order modulator, the input signal is sent to a difference block where the feedback signal is being subtracted from it. The resulting signal is sent to an integrator and the comparator acts on the integrator’s output. The comparator compares a reference voltage with the integrator’s output and generates a “high” or “low,” accordingly. In turn, the sub-DAC uses the output of the sub-ADC and generates one of the two available reference voltages. This reference voltage is passed to the difference block to be subtracted from the input again. This feedback forces the DAC’s output average to be equal to the input signal. The DAC’s output is an analog representation of its input, which is the modulator’s output. 4. In a typical first-order modulator, the input signal is sent to a difference block where the feedback signal is being subtracted from it. The resulting signal is sent to an integrator and the comparator acts on the integrator’s output. The comparator compares a reference voltage with the integrator’s output and generates a “high” or “low,” accordingly. In turn, the sub-DAC uses the output of the sub-ADC and generates one of the two available reference voltages. This reference voltage is passed to the difference block to be subtracted from the input again. This feedback forces the DAC’s output average to be equal to the input signal. The DAC’s output is an analog representation of its input, which is the modulator’s output.](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_FIG4.gif)
4.在一个典型的一阶Σ-Δ调制器中,输入信号被送入一个差分单元,在其中与反馈信号相减。之后信号进入积分器,比较器作用于积分器的输出。比较器将一个基准电压与积分器的输出比较并相应地输出高/低电平。反过来,子DAC又根据ADC的输出产生两个基准电压,并送入差分单元与输入再次相减。这个反馈迫使DAC的输出平均值与输入信号相等。DAC的输出是其输入的模拟表征,也是调制器的输出。(限于自身水平这段翻译很难得明了,就我自己的理解简而言之,积分器累积DAC输出平均值与输入信号的误差,并通过负反馈将该误差逐渐降低,最终使得DAC输出平均值趋向于输入信号。——译者注)
过采样对于信噪比(SNR)的影响
过采样提升了信噪比(signal-to-noise ratio ,SNR),当噪声功率降低时,可以预见SNR将提高。定量地看,对于非过采样变换器而言,其量化噪声由式二给出,它的由量化噪声决定的理论SNR值可以用输入信号和噪声信号之比表示:![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Eq10.gif)
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Eq11.gif)
其中N为变换器的位数。式(6)表示了过采样变换器的噪声功率,通过式(6)和式(10),对于过采样率为OSR的变换器的SNR可以计算如下:
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/08/0808EEsigmadelta_Eq12_0.jpg)
高阶调制器对信噪比的影响
通过高阶调制,Σ-Δ调制器还能进一步提升SNR。二阶Σ-Δ调制器每增加一倍的采样率就可以提升15dB的SNR。一般来说,采样率每翻一倍,信噪比得到的提升是每二倍采样率。式(13)也呈现了对于一阶调制器(其L = 1),其采样率每翻一倍就有9dB的信噪比提升。对于OSR相同的二阶调制器(其L = 2),该单位信噪比提升增加到15dB,也就是说,调制器每增加一阶,就有额外6dB的单位信噪比提升。
高阶调制器
因为调制器的输出是比特流,对其输出的可视化和验证正确性较为困难。(见图5和表格)![5. In a conceptual diagram for a first-order modulator, the input voltage to the modulator is 1 V, and the DAC VRefs are ±2.5 V. The table shows how the voltages are calculated and passed around within the modulator to create the resulting bit stream. 5. In a conceptual diagram for a first-order modulator, the input voltage to the modulator is 1 V, and the DAC VRefs are ±2.5 V. The table shows how the voltages are calculated and passed around within the modulator to create the resulting bit stream.](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_FIG5.gif)
5.在这个一阶调制器的概念图中,调制器输入为1V,DAC的两个基准电压(VRef)为±2.5 V。下表展示了电压在调制器中是如何被计算和传递以产生输出比特流的。
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_TABLE1.gif)
例如,通过逐次读取比较器的输出,我们得到了编码10111011,该例中的满量程是(2.5 – (–2 .5)) = 5 V。
在5 V的范围内,因为下基准是–2 .5V,1V的信号将比下基准高出3.5 V ,相当于3.5/5 = 0.7倍的满量程。生成的编码(HLHHHLHH 或 10111011)有6个高位和2个低位,所以八分之六的比特流编码是高位。因此,平均值是6/8 = 0.75。该平均值接近于实际的输入(0.7)。
如果继续重复操作,得到该表格中更多的数位,均值将越来越接近0.7。对于这种调制器,显然当输入接近上基准(+VRef)时,调制器输出更多的高位,当输入接近下基准(–VRef)时,调制器输出更多的低位。一个典型的正弦波输入产生一串在两个峰值(指正负峰值——译者注)处有更多的高位和低位的编码;而当输入趋近于中值时,输出的1和0的数量变得相近。
![6. A sine wave with resulting bit-stream out of a first-order modulator shows the various density of ones and zeros. 6. A sine wave with resulting bit-stream out of a first-order modulator shows the various density of ones and zeros.](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Fig6.jpg)
通常,调制器的阶数大于一。
![7. The order of modulator dictates the order of filter that follows. Generally, the order of the filter is equal to the order of modulator, plus one. 7. The order of modulator dictates the order of filter that follows. Generally, the order of the filter is equal to the order of modulator, plus one.](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EesigmadeltaFig7.gif)
7. 调制器的阶数决定了之后滤波器的阶数。一般来说滤波器的阶数等于调制器的阶数或阶数加一。
一个六阶调制器和其后的预选滤波器组成了一个24位的Σ-Δ ADC,并产生了该输出。同上,当输入幅度上升时,调制器产生更多的1,当输入趋近最小值时,产生更多0 (Fig. 8)。
![8. The bit stream output by the model of a sixth-order modulator is followed by a decimation filter to form a 24-bit delta-sigma ADC, resulting in this output. Again, as the input amplitude is increased, that the modulator generates more ones, and, moving toward the lowest voltage of the input, more zeros. 8. The bit stream output by the model of a sixth-order modulator is followed by a decimation filter to form a 24-bit delta-sigma ADC, resulting in this output. Again, as the input amplitude is increased, that the modulator generates more ones, and, moving toward the lowest voltage of the input, more zeros.](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Fig8_0.jpg)
8.(该段图注与上文相同,故略——译者注)。
引用
1. Delta-Sigma Data Converters; Theroy, Design, and Simulation, S.R. Norseworthy, R. Schreier, G.C. Temes, Wiley Interscience, 1997.
2. “A Sigma-Delta Modulator as an A/D Converter,” R.J. Van de Plassche, IEEE Transactions on Circuits and Systems, Vol. CAS-25, July 1978, pp. 510-514.
3. “Principles of Oversampling A/D Conversion,” Max W. Hauser, Journal Audio Engineering Society, Vol. 39, No. 1/2, January/February 1991, pp. 3-26.
4. “On Design & Implementation of a Decimation Filter for Multi-standard Wireless Transceivers,” A. Ghaze & et al., IEEE Transactions of Wireless Communications, Vol. 1, No. 4, Oct. 02.
5. “Understanding Cascaded Integrator Comb Filters,”Richard Lyons, Embedded Systems Programming, March 2005, www.design-reuse.com/articles/10028/understanding-cascaded-integrator-comb-filters.html
6. “An Economical Class of Digital Filters for Decimation and Interpolation,” E.B. Hogenauer, IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 29, No. 2, April 1981, pp 155-162
7. “Design Tradeoffs for Linear Phase FIR Decimation Filters and ∑-∂ Modulators,” A. Blad, P. Lowenborg, H. Johansson, 14th European Signal Processing Conference, 2006
8. “Low power Decimation Filter Architectures for ∑-∂ ADCs,” Özge Gürsoy, Orkun Sağlamdemir, Mustafa Aktan, Selçuk Talay, Günhan Dündar
9. For more information on data converters, visit www.ti.com/dataconverters-ca.
![](https://www.electronicdesign.com/sites/electronicdesign.com/files/uploads/2013/07/0808EEsigmadelta_Loloee.jpg)