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  • Chisel 学习笔记(三)

    Chisel 学习笔记(三)

    Chisel example、测试、verilog生成

    样例模块

    package Passthrough
    import chisel3._
    class MAC extends Module{
      val io = IO(new Bundle{
        val in_a = Input(UInt(4.W))
        val in_b = Input(UInt(4.W))
        val in_c = Input(UInt(4.W))
        val out = Output(UInt(8.W))
      })
    
      io.out := io.in_a * io.in_b + io.in_c
    
    }
    

    对模块进行测试

    package Passthrough
    import chisel3._
    import chisel3.iotesters.{Driver, PeekPokeTester}
    
    //测试样例如下所示
    class MACTester(c: MAC) extends PeekPokeTester(c) {
      val cycles = 100
      import scala.util.Random
      for (i <- 0 until cycles) {
        val in_a = Random.nextInt(16)
        val in_b = Random.nextInt(16)
        val in_c = Random.nextInt(16)
        poke(c.io.in_a, in_a)
        poke(c.io.in_b, in_b)
        poke(c.io.in_c, in_c)
        expect(c.io.out, in_a*in_b+in_c)
      }
    
    }
    
    //测试类如下所示
    class test{
    	assert(Driver(() => new MAC) {c => new MACTester(c)})
    	println("SUCCESS!!")
    }
    
    //运行测试
    object RunAppDemo {
      def main(args:Array[String]) {
        new test
      }
    }
    

    转换成verilog

    经过测试后,将上述模块转换生成verilog的代码如下

    object Main {
      def main(args: Array[String]): Unit = {
        println("Generating the Adder hardware")
        chisel3.Driver.execute(Array("--target-dir", "generated"), () => new MAC)
      }
    }
    
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  • 原文地址:https://www.cnblogs.com/JamesDYX/p/10072892.html
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