`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer: connor jiao // Create Date: 21:42 2020/8/5 // Design Name: // Module Name: // Function : //用计数器设计一个带am/pm的12小时时钟。该计数器通过一个CLK进行计时,用ena使能信号来驱动时钟的递增。 //reset信号将时钟复位为12:00 AM。 信号pm为0代表AM,为1代表PM。 //hh、mm和ss由两个BCD计数器构成hours(01~12), minutes(00~59) , second(00~59)。 //Reset信号比enable信号有更高的优先级,即使没有enable信号也可以进行复位操作。 // Revision 0.01 - File Created // Additional Comments: ////////////////////////////////////////////////////////////////////////////////// module top_module( input clk, input reset, input ena, output reg pm, output reg [7:0] hh, output reg [7:0] mm, output reg [7:0] ss); always@(posedge clk) if(reset) ss<='d0; else if(ena) if(ss==8'h59) ss<='d0; else if(ss[3:0]=='d9)begin ss[3:0]<='d0; ss[7:4]<=ss[7:4]+1'b1; end else begin ss[7:4]<=ss[7:4]; ss[3:0]<=ss[3:0]+1'b1; end else ss<=ss; always@(posedge clk) begin if(reset) mm<='d0; else if(ena&&ss==8'h59) if(mm=='h59) mm<='d0; else begin if(mm[3:0]=='d9)begin mm[3:0]<='d0; mm[7:4]<=mm[7:4]+1'b1; end else begin mm[3:0]<=mm[3:0]+1'b1; mm[7:4]<=mm[7:4]; end end else mm<=mm; end always@(posedge clk) begin if(reset) hh<=8'h12; else begin if(ena&&mm==8'h59&&ss==8'h59) if(hh==8'h12) hh<='d1; else begin if(hh[3:0]=='d9)begin hh[3:0]<='d0; hh[7:4]<=hh[7:4]+1'b1; end else begin hh[3:0]<=hh[3:0]+1'b1; hh[7:4]<=hh[7:4]; end end else hh<=hh; end end always@(posedge clk) begin if(reset) pm<=1'b0; else if(ena&&hh==8'h11&&mm==8'h59&&ss==8'h59) pm<=~pm; else pm<=pm; end endmodule