http://hi.baidu.com/xinchao628/blog/item/07e7a088a063faa70f244417.html
The clock tree sinks are the synchronous points of a clock tree.astro clock tree synthesis identifies the following pins as clock tree sinks.
.sequential cells'clock port with trigger edge information
.user-defined synchronous pins with tha ataDefineSyncPin or ataDefineSyncPort command
if you are not sure whether the clock ports of sequential cells in your library have trigger edge information,review your library preparation or use the auDumpCLF command to write a text file.in the file,you must have defineTimingTLU statemates with the following keywords for all sequential cell,
.setup_rising
.setup_falling
,hold_rising
.hold_falling
.clock_rising
.clock_falling
note:
if a sequential cell is defined as a clock-gating intergated cell with the dbSetLModeSubType command,or its output port has a create_generated_clock defined,its clock port is not treated as a clock sink(synchronous)pin,even if it has trgger edge information.astro clock tree synthesis traverses that pin and synthesize clock trees beyond that pin.
if you want to synchronize a nonclock pin-such as a combination logic gate's pin,a macro's pin,or a sequential gate's set/reset pin --you must define it as a synvhronous pin explicitly ,using the dbDefineSyncPin or dbDefineSyncPort command,the dbDefineSyncPin command is used for the instance ,whereas ,the dbDefineSyncPort command is used for the master.
review your library prepartion and design preparation to make sure your synchronous port and synchronous pin definitions are completed.
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