write-back/write-through/write-allocate/write-no-allocate
CPU读Cache时
●若hit，则CPU直接从Cache中读取数据即可。
●若miss，有两种处理方式：
>Read through，即直接从内存中读取数据；
>Read allocate，先把数据读取到Cache中，再从Cache中读数据。
写操作
先检查cache里是否有对应数据，如果有（write hit）：
根据是write-back还是write-through来具体操作：
write-back：将数据更新到cache，并不更新到内存（DRAM），待后续flush cache时存入内存；
write-through：数据同时会更新到cache和内存；
如果没有（write miss）：
根据是write-allocate或是write-no-allocate：
write-allocate：将要写入的位置从内存读到cache，然后按照上述write hit继续操作；
write-no-allocate：不会将要写入的数据从内存读到cache，直接将要写的数据写入内存。
transient attribute
Another new memory attribute feature in the Armv8-M architecture is that Normal memory has a new Transient attribute. If an address region is marked as Transient it means the data within is unlikely to be frequently used. A cache design could, therefore, utilize this information to prioritize transient data for cacheline evictions. A cacheline eviction operation is needed when the processor needs to store a new piece of data into the cache but all of the cache-ways of the corresponding cache index have already been used by older valid data. In the case of the Cortex-M23 and Cortex-M33 processors, this attribute is not used as (a) there is no data cache support, and (b) the AHB interface does not have any signal for transient indication. Please note, even when an Armv8-M processor has a data cache transient support, is an optional feature. This is because this feature increases the SRAM area needed for cache tags and might, therefore, not be desirable for some designs.
from: https://www.sciencedirect.com/topics/engineering/memory-attribute
device memory attributes
https://blog.csdn.net/shenhuxi_yu/article/details/90617675
https://zhuanlan.zhihu.com/p/124946496