直接测频法

module    cepin(
        clk,rst_n,
        ad_data,ad_clk,cnt_ms,
        pinlv,cepin_buffer
);

input                clk;
input                rst_n;
input        [9:0]    ad_data;
output                ad_clk;
output        [39:0]    pinlv;
output reg    [23:0]    cepin_buffer;
output reg    [23:0]    cnt_ms;
assign        ad_clk =~ clk;

//计数
parameter            CE_WAN = 24'd10_000_000;
reg                    flag_cnt;
always @(posedge clk or negedge rst_n)
    if(!rst_n)
        cnt_ms <= 'd0;
    else if(flag_cnt)
        cnt_ms <= 'd0;
    else
        cnt_ms <= cnt_ms + 1'b1;
//检测上升沿
reg            [9:0]    ad_data_r;
reg            [2:0]    state;
reg            [23:0]    cnt_cepin;
always @(posedge clk or negedge    rst_n)
    if(!rst_n)begin
        state <= 'd0;
        ad_data_r <= ad_data;
        cnt_cepin <= 'd0;
        cepin_buffer <= 'd0;
    end
    else
        case(state)
        3'd0:begin
            ad_data_r <= ad_data;
            if(ad_data_r < ad_data)
                state <= 3'd1;
            else
                state <= 3'd0;
        end
        3'd1:begin
            ad_data_r <= ad_data;
            if(ad_data_r > ad_data)
                state <= 3'd2;
            else
                state <= 3'd1;
        end
        3'd2:begin
            if(cnt_ms > CE_WAN)begin
                cepin_buffer <= cnt_cepin;
                cnt_cepin <= 'd0;
                flag_cnt <= 1'd1;
            end
            else begin
                cepin_buffer <= cepin_buffer;
                cnt_cepin <= cnt_cepin + 1'b1;
                flag_cnt <= 'd0;
            end
            state <= 3'd0;
        end
        endcase


assign        pinlv =  5*cepin_buffer;
//assign    pinlv = CE_P / cnt_r;

endmodule

.直接测频法：由时基信号形成闸门，对被测信号进行计数。当闸门宽度为1s时可直接从计数器读出被测信号频率。计数值存在正负一个脉冲的误差是可能的，故此法的绝对误差就是1Hz（对1s宽的闸门而言）。其相对误差则随着被测频率的升高而降低，故此法适于测高频而不适于测低频。