(原创)DE2数字逻辑实验——Mechanics of DE2 ProjectsAltera DE2 Project Diglab1(DE2)(Quartus ii)(Verilog)

Altera DE2 Project Diglab1

Download: design files

For a discussion of the steps involved in ptogramming the DE2 board, see Mechanics of Altera DE2 Board Programming

Top-Level Entity

The module declaration names the DE2 ports we think we might want to use. The names are the same as those used in DE2_pin_assignments.csv.

module diglab1(
// Clock Input (50 MHz)
input  CLOCK_50,
//  Push Buttons
input  [3:0]  KEY,
//  DPDT Switches
input  [17:0]  SW,
//  7-SEG Displays
output  [6:0] HEX0, HEX1, HEX2, HEX3,
HEX4, HEX5, HEX6, HEX7,
//  LEDs
output  [8:0]  LEDG,  //  LED Green[8:0]
output  [17:0]  LEDR, //  LED Red[17:0]
//  GPIO Connections
inout  [35:0]  GPIO_0, GPIO_1
);

External I/O Connections

There are two 36-pin headers on the DE2 board. They are mapped to inout pins on the Altera Cyclone II FPGA. They are not used in this project, so we set them to tri-state (high Z)

//  set all inout ports to tri-state
assign  GPIO_0    =  36'hzzzzzzzzz;
assign  GPIO_1    =  36'hzzzzzzzzz;

LED Connections

Connect dip switches to red LEDs

assign LEDR[17:0] = SW[17:0];

Turn off green LEDs

assign LEDG[8:0] = 0;

7-Segment Displays

We declare a 16-bit vector of bits, and assign groups of four bits (nibbles) to four of the 7-segment displays, which will convert the inputs to the proper segments to display the corresponding hex digits

reg [15:0] A;
// map to 7-segment displays
hex_7seg dsp0(A[3:0],HEX0);
hex_7seg dsp1(A[7:4],HEX1);
hex_7seg dsp2(A[11:8],HEX2);
hex_7seg dsp3(A[15:12],HEX3);

We say that this code instantiates four hex-7seg modules.

The following code segment shows how to blank unused 7-segment digits. The 7-segment displays use active low ?if you want to turn off a segment, set it high.

wire [6:0] blank = ~7'h00;
// blank remaining digits
assign HEX4 = blank;
assign HEX5 = blank;
assign HEX6 = blank;
assign HEX7 = blank;

User Interface

When the user presses KEY3, the action creates a high-to-low transition on the corresponding port. We choose to capture (latch) the configure of dip switches 15 ?0 into the A register. This value will simultaneously be displayed on the assigned 7-segment displays.

// control (set) value of A, signal with KEY3
always @(negedge KEY[3])
A <= SW[15:0];

7-Segment Display Logic

// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
always @ (hex_digit)
case (hex_digit)
4'h0: seg = ~7'h3F;
4'h1: seg = ~7'h06;     // ---a----
4'h2: seg = ~7'h5B;     // |      |
4'h3: seg = ~7'h4F;     // f      b
4'h4: seg = ~7'h66;     // |      |
4'h5: seg = ~7'h6D;     // ---g----
4'h6: seg = ~7'h7D;     // |      |
4'h7: seg = ~7'h07;     // e      c
4'h8: seg = ~7'h7F;     // |      |
4'h9: seg = ~7'h67;     // ---d----

See: hex_7seg.v

Activities

1. Map 7 dip switches directly to the segments of one of the 7-segment displays. Now you can design your own patterns. For example you could change the line for HEX7 to

      assign HEX7 = ~SW[6:0];
       

2. Program the display so that the first four 7-segment displays spell out a word: like HELP?or Food?
3. Modify the starting program so that KEY3 enters the 8-bit value from SW[7:0] and displays it on HEX7-HEX6, KEY2 enters the 8-bit value from SW[7:0] and displays it on HEX5-HEX4, and KEY1 generates the logical and of A and B and displays the result in HEX1-HEX0. Blank the digits HEX3-HEX2.

References

Verilog source and Quartus compilation report