FPGA自计数六位共阳极数码管动态显示2（调用task的方法）

`timescale 1ns/1ps
module adc_dis(
               clk ,
               rst_n ,       
               sm_seg ,
               sm_bit
                );
                    
input clk;//50HZ
input rst_n;
output[7:0] sm_seg;//段选
output[5:0] sm_bit;//位选

reg [7:0] sm_seg;
reg [5:0] sm_bit;
reg [31:0] count;
reg [31:0] count2;
reg [3:0] i;//数码管位数
reg clk1, clk2;
reg [3:0]ge,shi,bai,qian,wan,swan;
reg [7:0] ge_reg,shi_reg,bai_reg,qian_reg,wan_reg,swan_reg;

parameter//共阳极
        led_GYA0 = 8'hc0,     //'0'  
        led_GYA1 = 8'hf9,     //'1'
        led_GYA2 = 8'ha4,     //'2'
        led_GYA3 = 8'hb0,     //'3'
        led_GYA4 = 8'h99,     //'4'
        led_GYA5 = 8'h92,     //'5'
        led_GYA6 = 8'h82,     //'6'
        led_GYA7 = 8'hf8,     //'7'
        led_GYA8 = 8'h80,     //'8'
        led_GYA9 = 8'h90;     //'9'

/****************分频1S*****************/        
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin //同步复位
           clk2  <= 1'b0;
           count2 <= 32'b0;
           end
else if(count2 == 32'd24999999) begin //高低电平转换 5*10^7*20ns=10^9ns=1s
                                clk2 <= ~clk2;
                                count2 <= 32'b0;
                                end
else begin
     count2 <= count2 + 1'b1; //计数
     end
 end
        
/******************计数*********************/
always@(posedge clk2 or negedge rst_n) begin//个位处理
if(!rst_n) begin
           ge <= 4'b0000;
           shi <= 4'b0000;
           bai <= 4'b0000;
           qian <= 4'b0000;
           wan <= 4'b0000;
           swan <= 4'b0000; 
           end
else if(ge == 4'b1010) begin //个位等于10
                       ge  = 4'b0000;
                       shi = shi + 1'b1;
                       if(shi == 4'b1010) begin//十位等于10
                                          shi = 4'b0000;
                                          bai = bai + 1'b1;
                                          if(bai == 4'b1010) begin//百位等于10
                                                             bai  = 4'b0000;
                                                             qian = qian + 1'b1;
                                                             if(qian == 4'b1010) begin//千位等于10
                                                                                 qian = 4'b0000;
                                                                                 wan  = wan + 1'b1;
                                                                                 if(wan == 4'b1010) begin//万位等于10
                                                                                                    wan  = 4'b0000;
                                                                                                    swan = swan + 1'b1;
                                                                                                    if(swan == 4'b1010) begin//十万位等于10
                                                                                                                        ge <= 4'b0000;
                                                                                                                        shi <= 4'b0000;
                                                                                                                        bai <= 4'b0000;
                                                                                                                        qian <= 4'b0000;
                                                                                                                        wan <= 4'b0000;
                                                                                                                        swan <= 4'b0000; 
                                                                                                                        end
                                                                                                    end 
                                                                                 end
                                                             end 
                                        end
                         end
else  begin
        ge <= ge + 1'b1;
        end
        
end
                          
/***************编码*******************/
always@(posedge clk2 or negedge rst_n) begin
//case(ge)
//     4'b0000: ge_reg <= led_GYA0;
//     4'b0001: ge_reg <= led_GYA1;
//     4'b0010: ge_reg <= led_GYA2;
//     4'b0011: ge_reg <= led_GYA3;
//     4'b0100: ge_reg <= led_GYA4;
//     4'b0101: ge_reg <= led_GYA5;
//     4'b0110: ge_reg <= led_GYA6;
//     4'b0111: ge_reg <= led_GYA7;
//     4'b1000: ge_reg <= led_GYA8; 
//     4'b1001: ge_reg <= led_GYA9;
//     default: ge_reg <= led_GYA0; 
//endcase
//      
//case(shi)
//     4'b0000: shi_reg <= led_GYA0;
//     4'b0001: shi_reg <= led_GYA1;
//     4'b0010: shi_reg <= led_GYA2;
//     4'b0011: shi_reg <= led_GYA3;
//     4'b0100: shi_reg <= led_GYA4;
//     4'b0101: shi_reg <= led_GYA5;
//     4'b0110: shi_reg <= led_GYA6;
//     4'b0111: shi_reg <= led_GYA7;
//     4'b1000: shi_reg <= led_GYA8; 
//     4'b1001: shi_reg <= led_GYA9;
//     default: shi_reg <= led_GYA0; 
//endcase
//
//case(bai)
//     4'b0000: bai_reg <= led_GYA0;
//     4'b0001: bai_reg <= led_GYA1;
//     4'b0010: bai_reg <= led_GYA2;
//     4'b0011: bai_reg <= led_GYA3;
//     4'b0100: bai_reg <= led_GYA4;
//     4'b0101: bai_reg <= led_GYA5;
//     4'b0110: bai_reg <= led_GYA6;
//     4'b0111: bai_reg <= led_GYA7;
//     4'b1000: bai_reg <= led_GYA8; 
//     4'b1001: bai_reg <= led_GYA9;
//     default: bai_reg <= led_GYA0;
//endcase
//      
//case(qian)
//     4'b0000: qian_reg <= led_GYA0;
//     4'b0001: qian_reg <= led_GYA1;
//     4'b0010: qian_reg <= led_GYA2;
//     4'b0011: qian_reg <= led_GYA3;
//     4'b0100: qian_reg <= led_GYA4;
//     4'b0101: qian_reg <= led_GYA5;
//     4'b0110: qian_reg <= led_GYA6;
//     4'b0111: qian_reg <= led_GYA7;
//     4'b1000: qian_reg <= led_GYA8; 
//     4'b1001: qian_reg <= led_GYA9;
//     default: qian_reg <= led_GYA0;
//endcase
//      
//case(wan)
//     4'b0000: wan_reg <= led_GYA0;
//     4'b0001: wan_reg <= led_GYA1;
//     4'b0010: wan_reg <= led_GYA2;
//     4'b0011: wan_reg <= led_GYA3;
//     4'b0100: wan_reg <= led_GYA4;
//     4'b0101: wan_reg <= led_GYA5;
//     4'b0110: wan_reg <= led_GYA6;
//     4'b0111: wan_reg <= led_GYA7;
//     4'b1000: wan_reg <= led_GYA8; 
//     4'b1001: wan_reg <= led_GYA9;
//     default: wan_reg <= led_GYA0;
//endcase
//      
//case(swan)
//     4'b0000: swan_reg <= led_GYA0;
//     4'b0001: swan_reg <= led_GYA1;
//     4'b0010: swan_reg <= led_GYA2;
//     4'b0011: swan_reg <= led_GYA3;
//     4'b0100: swan_reg <= led_GYA4;
//     4'b0101: swan_reg <= led_GYA5;
//     4'b0110: swan_reg <= led_GYA6;
//     4'b0111: swan_reg <= led_GYA7;
//     4'b1000: swan_reg <= led_GYA8; 
//     4'b1001: swan_reg <= led_GYA9;
//     default: swan_reg <= led_GYA0;
//endcase
BIANMA(ge, ge_reg);
BIANMA(shi, shi_reg);
BIANMA(bai, bai_reg);
BIANMA(qian, qian_reg);
BIANMA(wan, wan_reg);
BIANMA(swan, swan_reg);

end
        
/****************分频1MS*****************/        
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin //同步复位
           clk1  <= 1'b0;
           count <= 1'b0;
           end
else if(count == 32'd24999)begin //高低电平转换 25000*20=500000ns=0.5ms
                           clk1 <= ~clk1;
                           count <= 1'b0;
                           end
else begin
     count <= count + 1'b1; //计数
     end
 end

/************数码管位数循环****************/    
always@(posedge clk1 or negedge rst_n) begin

if(!rst_n) begin //同步复位
            i <= 4'b0000;
            end
else if(i == 4'b0101) begin 
                      i <= 4'b0000;
                      end
212 else begin
     i <= i + 1'b1;
     end
end

/************数码管显示****************/
always@(posedge clk1 or negedge rst_n) begin  
        case(i)
            4'b0000: begin sm_seg <= ge_reg;    sm_bit <= 6'b01_1111;  end
            4'b0001: begin sm_seg <= shi_reg;   sm_bit <= 6'b10_1111;  end
            4'b0010: begin sm_seg <= bai_reg;   sm_bit <= 6'b11_0111;  end
            4'b0011: begin sm_seg <= qian_reg;  sm_bit <= 6'b11_1011;  end
            4'b0100: begin sm_seg <= wan_reg;   sm_bit <= 6'b11_1101;  end
            4'b0101: begin sm_seg <= swan_reg;  sm_bit <= 6'b11_1110;  end
            default: begin sm_seg <= led_GYA0;  sm_bit <= 6'b11_1111;  end 
        endcase
   end         

task BIANMA;
input[3:0] wei;//哪个位
output[7:0] wei_reg; //这个位上此时的数据
reg [7:0] wei_reg;
begin
case(wei)
      4'b0000: wei_reg <= led_GYA0;
      4'b0001: wei_reg <= led_GYA1;
      4'b0010: wei_reg <= led_GYA2;
      4'b0011: wei_reg <= led_GYA3;
      4'b0100: wei_reg <= led_GYA4;
      4'b0101: wei_reg <= led_GYA5;
      4'b0110: wei_reg <= led_GYA6;
      4'b0111: wei_reg <= led_GYA7;
      4'b1000: wei_reg <= led_GYA8; 
      4'b1001: wei_reg <= led_GYA9;
      default: wei_reg <= led_GYA0;
endcase
end
endtask
    
endmodule