mig_7series_v4_0_data_gen_chk

mig_7series_v4_0_data_gen_chk

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2018/07/17 09:57:04
// Design Name: 
// Module Name: mig_7series_v4_0_data_gen_chk
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mig_7series_v4_0_data_gen_chk # (

    parameter C_AXI_DATA_WIDTH     = 32 // Width of the AXI write and read data

    )
(

    input            clk,
    input            data_en,
    input  [2:0]  data_pattern,
    input            pattern_init,
    input  [31:0] prbs_seed_i,
    input         wrd_cntr_rst,
    input         rdata_vld,
    input [C_AXI_DATA_WIDTH-1:0]   rdata,
    input [C_AXI_DATA_WIDTH/8-1:0] rdata_bvld,

    output reg [31:0] data_o,           // generated data
    output reg [7:0]  wrd_cntr        // Word count output



);


//---------------------------------------------------------------

    // 产生数据
    reg [32:1] lfsr_q = 32'h0;
    always @(posedge clk)
    begin
        if(pattern_init)
        begin
            lfsr_q <= {prbs_seed_i + 32'h55555555};
        end

        else if(data_en)
        begin
            lfsr_q[32:9] <= lfsr_q[31:8];   
            lfsr_q[8]    <= lfsr_q[32] ^ lfsr_q[7];
            lfsr_q[7]    <= lfsr_q[32] ^ lfsr_q[6];
            lfsr_q[6:4]  <= lfsr_q[5:3];
            lfsr_q[3]    <= lfsr_q[32] ^ lfsr_q[2];
              lfsr_q[2]    <= lfsr_q[1] ;
              lfsr_q[1]    <= lfsr_q[32];
        end
    end

//---------------------------------------------------------------

    // 数据向左移
      reg [31:0] walk0 = 32'h0;    
    always @(posedge clk)
    begin
        if(pattern_init)
            walk0 <= 32'hFFFF_FFFE;

        else if(data_en)
            walk0 <= {walk0[30:0],walk0[31]};
    end

//---------------------------------------------------------------

    //数据向左移
      reg [31:0] walk1 = 32'h0;
      always @(posedge clk)
      begin
        if (pattern_init)
              walk1 <= 32'h0000_0001;

        else if (data_en)
             walk1 <= {walk1[30:0],walk1[31]};
    end

//---------------------------------------------------------------

    reg [31:0] prbs;
    always @(*) 
    begin
        prbs = lfsr_q[32:1];
      end

//---------------------------------------------------------------

    // 选择输出数据的模式
    always @(*) 
    begin
        case (data_pattern)
          3'b001: data_o = prbs; // PRBS pattern
          3'b010: data_o = walk0; // Walking zeros
          3'b011: data_o = walk1; // Walking ones
          3'b100: data_o = 32'hFFFF_FFFF; // All ones
          3'b101: data_o = 32'h0000_0000; // All zeros
          default: data_o = 32'h5A5A_A5A5;
        endcase
      end

//---------------------------------------------------------------

    //数据计数器
    always @(posedge clk)
    begin
          if (wrd_cntr_rst)
            wrd_cntr <= 8'h00;

        else if (rdata_vld)
            wrd_cntr <= wrd_cntr + 8'h01;
    end


//---------------------------------------------------------------

//此段代码是对输出的数据与读进来数据进行对比，如果不一致，则会产生错误标志位

    reg [C_AXI_DATA_WIDTH/32-1:0]   msmatch_err_sig;

    genvar i;
    generate
        begin: data_check
            for(i = 0; i <= (C_AXI_DATA_WIDTH/32-1); i=i+1)
            begin:gen_data_check
                always @(posedge clk)
                    if(wrd_cntr_rst)
                        msmatch_err_sig[i] <= 1'b0;
                    else if( rdata_vld &
                            (    (rdata[((i*32)+7):i*32] != data_o[7:0] & rdata_bvld[(i*4)]) |
                            (rdata[((i*32)+15):((i*32)+8)] != data_o[15:8] & rdata_bvld[(i*4)+1]) |
                            (rdata[((i*32)+23):((i*32)+16)] != data_o[23:16] & rdata_bvld[(i*4)+2]) |
                            (rdata[((i*32)+31):((i*32)+24)] != data_o[31:24] & rdata_bvld[(i*4)+3])  )
                        )
                        msmatch_err_sig[i] <= 1'b1;
                    else 
                        msmatch_err_sig[i] <= 1'b0;
                
            end    
        end
        
    endgenerate

    assign msmatch_err = |msmatch_err_sig;


endmodule




/*
add_force {/mig_7series_v4_0_data_gen_chk/clk} -radix hex {1 0ns} {0 50000ps} -repeat_every 100000ps
add_force {/mig_7series_v4_0_data_gen_chk/pattern_init} -radix hex {0 0ns} {1 200ns} {0 300ns}
add_force {/mig_7series_v4_0_data_gen_chk/prbs_seed_i} -radix hex {00000001 0ns}
add_force {/mig_7series_v4_0_data_gen_chk/data_en} -radix hex {0 0ns} {1 500ns} {0 600ns} {1 800ns} {0 900ns}



*/