1. 典型的Verilog模块结构
module M (P1,P2,P3,P4);
input P1,P2;
output [7:0] P3;
inout P4;
reg [7:0] R1,M1 [1:1024];
wire W1, W2, W3, W4;
parameter C1 = "This is a string";
initial
begin : 块名
//声明语句
end
always@ (触发事件)
begin
//声明语句
end
//连续赋值语句
assign W1 = Expression;
wire (Strong1, Weak0) [3:0] #(2,3) W2 = Expression;
//模块实例引用
COMP U1 (W3, W4);
COMP U2 (.P1(W3), .P2(W4));
task T1; //任务定义
input A1;
inout A2;
output A3;
begin
//声明语句
end
endtask
function [7:0] F1; //函数定义
input A1;
begin
//声明语句
F1 = 表达式；
end
endfunction
endmodule //模块结束
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////我是分隔符/////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////
2.声明语句
#delay
wait (Expression)
@(A or B or C)
@(posedge Clk)
Reg= Expression;
Reg<= Expression;
VectorReg[Bit] = Expression;
VectorReg[MSB:LSB] = Expression;
Memory[Addres] = Expression;
assign Reg = Expression;
deassign Reg;
TaskEnable(...);
disable TaskOrBlock;
EventName;
if (Condition)
...
else if (Condition)
...
else
...
case (Selection)
Choice1:
...
Choice2,Choice3:
...
default:
...
endcase
for (I=0; I<MAX; I=I+1)
...
repeat (8)
...
while (Condition)
...
forever
...