Cadence关于UVM的简单介绍，包括UVM的各个方面。有中文和英文两种版本。
UVM SV Basics 1 – Introduction
UVM SV Basics 2 – DUT Example
UVM SV Basics 3 – UVM Environment
UVM SV Basics 4 – Interface UVC
UVM SV Basics 5 – Collector
UVM SV Basics 6 – Monitor
UVM SV Basics 7 – Sequence Item
UVM SV Basics 8 – Sequence
UVM SV Basics 9 – driver
UVM SV Basics 10 – Sequencer
UVM SV Basics 11 – Agent
UVM SV Basics 12 – Agent Type
UVM SV Basics 13 – Interface UVC Envrionment
UVM SV Basics 14 – Virtual Sequencer
UVM SV Basics 15 – Module UVC
UVM SV Basics 16 – Scoreboard
UVM SV Basics 17 – DUT Functional Coverage
UVM SV Basics 18 – Testbench
UVM SV Basics 19 – Test
UVM SV Basics 20 – Configuration
UVM SV Basics 21 – Factory
UVM SV Basics 22 – Phases
UVM SV Basics 23 – Objections
UVM SV Basics 24 – Virtual Interface
UVM SV Basics 25 – Class Library Overview
参考文献：
Cadence中国的视频页面