Pulse-width Modulation (PWM)
Pulse-width modulation (PWM) is a technique that modifies the duty-cycle of a pulsing signal to encode information or to control the amount of energy provided to a charge.
On the ConnectCore 6UL system-on-module there are:
- Eight PWM signals (from PWM1 to PWM8) available from the ConnectCore 6UL system-on-chip (multiplexed with other signals).
On the ConnectCore 6UL Starter Board:
- PWM1, PWM2, PWM3, and PWM4 are available on the expansion header.
On the ConnectCore 6UL SBC:
- PWM5 is connected to the parallel display and LVDS display connectors for backlight control.
Kernel configuration
You can manage the i.MX6UL PWM driver support through the following kernel configuration option:
- i.MX PWM support (CONFIG_PWM_IMX)
This option is enabled as built-in on the default ConnectCore 6UL kernel configuration file.
Platform driver mapping
The driver for the i.MX6UL PWM is located at:
|
File |
Description |
|---|---|
|
PWM driver |
Device tree bindings and customization
The i.MX6UL PWM interface is documented at Documentation/devicetree/bindings/pwm/imx-pwm.txt.
The device tree must contain entries for:
- The PWM interfaces
- The IOMUX
i.MX6UL PWM interfaces
Common i.MX6UL device tree
pwm1: pwm@02080000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_PWM1>,
<&clks IMX6UL_CLK_PWM1>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
};
pwm2: pwm@02084000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_DUMMY>,
<&clks IMX6UL_CLK_DUMMY>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
};
pwm3: pwm@02088000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_DUMMY>,
<&clks IMX6UL_CLK_DUMMY>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
};
pwm4: pwm@0208c000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_DUMMY>,
<&clks IMX6UL_CLK_DUMMY>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
};
pwm5: pwm@020f0000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020f0000 0x4000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_DUMMY>,
<&clks IMX6UL_CLK_DUMMY>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
};
pwm6: pwm@020f4000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020f4000 0x4000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_DUMMY>,
<&clks IMX6UL_CLK_DUMMY>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
};
pwm7: pwm@020f8000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020f8000 0x4000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_DUMMY>,
<&clks IMX6UL_CLK_DUMMY>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
};
pwm8: pwm@020fc000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020fc000 0x4000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_DUMMY>,
<&clks IMX6UL_CLK_DUMMY>;
clock-names = "ipg", "per";
#pwm-cells = <2>;
}
The common i.MX6UL device tree only defines the clock of PWM1 and uses a dummy clock source for the rest of PWM channels, which remain disabled. You must assign appropriate clocks to a PWM channel in order to use it.
Example: PWM5 as backlight on ConnectCore 6UL SBC
For example, PWM5 is being used for the display backlight control on the ConnectCore 6UL SBC Pro:
ConnectCore 6UL SBC Pro device tree
/ {
lcd_backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm5 0 50000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "disabled";
};
};
/* LCD backlight */
&pwm5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm5>;
clocks = <&clks IMX6UL_CLK_PWM5>,
<&clks IMX6UL_CLK_PWM5>;
status = "disabled";
};
Example: PWM4 on ConnectCore 6UL SBC Express
For example, PWM4 is available on the ConnectCore 6UL SBC Express expansion connector. You must configure the clocks for the PWM4 and a pinctrl handler:
ConnectCore 6UL Starter Board
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
clocks = <&clks IMX6UL_CLK_PWM4>,
<&clks IMX6UL_CLK_PWM4>;
};
IOMUX
Select appropriate IOMUX for the pad that's going to act as PWM channel on the ConnectCore 6UL SBC Pro:
ConnectCore 6UL SBC Pro device tree
pinctrl_pwm5: pwm5grp {
fsl,pins = <
MX6UL_PAD_NAND_DQS__PWM5_OUT 0x110b0
>;
};
For PWM4 on the ConnectCore 6UL SBC Express:
ConnectCore 6UL SBC Express
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x11080
>;
};
Depending on the frequency of the PWM signal and the hardware around it, you must enable the pad settings carefully (the numerical value following the IOMUX definition on the device tree). See Documentation/devicetree/bindings/pinctrl/fsl,imx6ul-pinctrl.txt for information about the different values. Also see the NXP application note AN5078 Influence of pin setting on system function and performance for additional information.
Using the PWM channels
Backlight control
Backlight PWM control is managed through backlight sysfs entries. To read the maximum allowed brightness level of the backlight:
~# cat /sys/class/backlight/backlight/max-brightness 7
To set a certain brightness value:
~# echo 4 > /sys/class/backlight/backlight/brightness
Control PWM signal from sysfs
Each of the eight PWM interfaces is registered in the system as a standalone PWM controller. Unless specifically disabled in the platform device tree, they are all enabled by default in the common i.MX6UL device tree.
The PWM interfaces appear under /sys/class/pwm:
~# ls /sys/class/pwm/ pwmchip0 pwmchip1 pwmchip2 pwmchip3 pwmchip4 pwmchip5 pwmchip6 pwmchip7
As with any other device in Linux, they start numbering with an index of 0, which corresponds to PWM1.
Each PWM interface only manages one PWM signal. You can confirm this by printing the value of npwm (number of PWM signals controlled by an interface):
~# cat /sys/class/pwm/pwmchip4/npwm 1
To access the PWM channel, export its index (0 since there is only one):
~# echo 0 > /sys/class/pwm/pwmchip4/export
Now you can access the PWM channel and configure its settings:
~# ls /sys/class/pwm/pwmchip4/pwm0/ duty_cycle enable period polarity power uevent
Period and duty cycle are given in nanoseconds. For example, for a 100 kHz signal with 50% duty cycle:
~# echo 10000 > /sys/class/pwm/pwmchip4/pwm0/period ~# echo 5000 > /sys/class/pwm/pwmchip4/pwm0/duty_cycle
To enable the PWM signal:
~# echo 1 > /sys/class/pwm/pwmchip4/pwm0/enable