ARM学习之S3C2440的bootloader代码分析（1）

;===========================================
; NAME: OPTION.A
; DESC: Configuration options for .S files
; HISTORY:
; 02.28.2002: ver 0.0
; 03.11.2003: ver 0.0    attached for 2440.
; jan E, 2004: ver0.03  modified for 2440A01.
;===========================================
;这个Option.inc文件主要是为设置时钟服务的，选择好分频系数
;Start address of each stacks,
_STACK_BASEADDRESS    EQU 0x33ff8000
_MMUTT_STARTADDRESS    EQU 0x33ff8000
_ISR_STARTADDRESS    EQU 0x33ffff00

;定义一个全局的逻辑变量，变初始化为TRUE
        GBLL     PLL_ON_START    
PLL_ON_START    SETL     {TRUE}

;定义一个全局的逻辑变量，变初始化为FALSE
        GBLL    ENDIAN_CHANGE
ENDIAN_CHANGE    SETL    {FALSE}

;定义一个全局的数字变量，变初始化为16
        GBLA    ENTRY_BUS_WIDTH
ENTRY_BUS_WIDTH    SETA    16


;BUSWIDTH = 16,32
        GBLA    BUSWIDTH    ;max. bus width for the GPIO configuration
BUSWIDTH    SETA    32

        GBLA    UCLK
UCLK    SETA    96000000;48000000

        GBLA    XTAL_SEL
        GBLA    FCLK
        GBLA    CPU_SEL

;(1) Select CPU        
;CPU_SEL    SETA    32440000    ; 32440000:2440X.
CPU_SEL    SETA    32440001    ; 32440001:2440A

;(2) Select XTaL
XTAL_SEL    SETA    12000000    
;XTAL_SEL    SETA    16934400

;(3) Select FCLK
;FCLK        SETA    296352000
;FCLK        SETA    271500000
;FCLK        SETA    100000000    
FCLK        SETA    240000000    
FCLK        SETA    280000000    
FCLK        SETA    320000000    
FCLK        SETA    360000000    
FCLK        SETA    400000000    

;(4) Select Clock Division (Fclk:Hclk:Pclk)
;CLKDIV_VAL    EQU    5    ; 0=1:1:1, 1=1:1:2, 2=1:2:2, 3=1:2:4, 4=1:4:4, 5=1:4:8, 6=1:3:3, 7=1:3:6.
;定义时钟比例
;--------------------------------------------
;下面根据外部晶振是12MMhz（else是16.9344Mhz),再根据我们的主时钟是（271.5MHz或304.8MHz），决定分频系数M_MDIV、M_PDIV、M_SDIV
;根据我们的USB时钟（48MHz或者96MHz），决定分频系数U_MDIV、U_PDIV、U_SDIV
;--------------------------------------------
;[是IF伪操作的同义词，|是ELSE伪操作的同义词，]是ENDIF伪操作的同义词
 [ XTAL_SEL = 12000000
 
    [ FCLK = 271500000
CLKDIV_VAL    EQU    7        ;1:3:6
M_MDIV        EQU    173        ;Fin=12.0MHz Fout=271.5MHz
M_PDIV        EQU    2
        [ CPU_SEL = 32440001
M_SDIV        EQU    2        ; 2440A
           |
M_SDIV        EQU    1        ; 2440X
           ]
    ]
    
    [ FCLK = 100000000
CLKDIV_VAL    EQU    0        ;1:1:1
M_MDIV        EQU    42        ;Fin=12.0MHz Fout=100MHz
M_PDIV        EQU    4
        [ CPU_SEL = 32440001
M_SDIV        EQU    1        ; 2440A
        |
M_SDIV        EQU    0        ; 2440X
        ]
    ]

    [ FCLK = 240000000
CLKDIV_VAL    EQU    4        ;1:4:4
M_MDIV        EQU    112        ;Fin=12.0MHz Fout=240MHz
M_PDIV        EQU    4
        [ CPU_SEL = 32440001
M_SDIV        EQU    1        ; 2440A
        |
M_SDIV        EQU    0        ; 2440X
        ]
    ]
    
    [ FCLK = 280000000
CLKDIV_VAL    EQU    4        ;1:4:4
M_MDIV        EQU    132        ;Fin=12.0MHz Fout=280MHz
M_PDIV        EQU    4
        [ CPU_SEL = 32440001
M_SDIV        EQU    1        ; 2440A
        |
M_SDIV        EQU    0        ; 2440X
        ]
    ]
    
    [ FCLK = 320000000
CLKDIV_VAL    EQU    5        ;1:4:8
M_MDIV        EQU    72        ;Fin=12.0MHz Fout=320MHz
M_PDIV        EQU    1
        [ CPU_SEL = 32440001
M_SDIV        EQU    1        ; 2440A
        |
M_SDIV        EQU    0        ; 2440X
        ]
    ]
    
    [ FCLK = 360000000
CLKDIV_VAL    EQU    5        ;1:4:8
M_MDIV        EQU    82        ;Fin=12.0MHz Fout=360MHz
M_PDIV        EQU    1
        [ CPU_SEL = 32440001
M_SDIV        EQU    1        ; 2440A
        |
M_SDIV        EQU    0        ; 2440X
        ]
    ]

    [ FCLK = 400000000
CLKDIV_VAL    EQU    5        ;1:4:8
M_MDIV        EQU    127        ;127
M_PDIV        EQU    2        ;2
        [ CPU_SEL = 32440001
M_SDIV        EQU    1        ; 2440A
        |
M_SDIV        EQU    0        ; 2440X
        ]
    ]
    
    [ UCLK = 48000000
U_MDIV        EQU    56        ;Fin=12.0MHz Fout=48MHz
U_PDIV        EQU    2
        [ CPU_SEL = 32440001
U_SDIV        EQU    2        ; 2440A
           |
U_SDIV        EQU    1        ; 2440X
           ]
    ]
    [ UCLK = 96000000
U_MDIV        EQU    56        ;Fin=12.0MHz Fout=96MHz
U_PDIV        EQU    2
        [ CPU_SEL = 32440001
U_SDIV        EQU    1        ; 2440A
           |
U_SDIV        EQU    0        ; 2440X
           ]

    ]

  |    ; else if XTAL_SEL = 16.9344Mhz

    [ FCLK = 266716800
M_MDIV        EQU    118    ;Fin=16.9344MHz
M_PDIV        EQU    2
        [ CPU_SEL = 32440001
M_SDIV        EQU    2        ; 2440A
        |
M_SDIV        EQU    1        ; 2440X
        ]
    ]
    
    [ FCLK = 296352000
M_MDIV        EQU    97    ;Fin=16.9344MHz
M_PDIV        EQU    1
        [ CPU_SEL = 32440001
M_SDIV        EQU    2        ; 2440A
        |
M_SDIV        EQU    1        ; 2440X
        ]
    ]
    [ FCLK = 541900800
M_MDIV        EQU    120    ;Fin=16.9344MHz
M_PDIV        EQU    2
        [ CPU_SEL = 32440001
M_SDIV        EQU    1        ; 2440A
        |
M_SDIV        EQU    0        ; 2440X
        ]
    ]
    
    [ UCLK = 48000000
U_MDIV        EQU    60    ;Fin=16.9344MHz Fout=48MHz
U_PDIV        EQU    4
        [ CPU_SEL = 32440001
U_SDIV        EQU    2        ; 2440A
           |
U_SDIV        EQU    1        ; 2440X
           ]
       ]
    [ UCLK = 96000000
U_MDIV        EQU    60    ;Fin=16.9344MHz Fout=96MHz
U_PDIV        EQU    4
        [ CPU_SEL = 32440001
U_SDIV        EQU    1        ; 2440A
           |
U_SDIV        EQU    0        ; 2440X
           ]
    ]
    
   ]    ; end of if XTAL_SEL = 12000000.
  



    END

PLL_ON_START; 设置PLL 初始状态

ENDIAN_CHANGE; 选择ENDIAN，具体值应该根据硬件的设置来定

ENTRY_BUS_WIDTH; 配置入口总线宽度

BUSWIDTH; 配置GPIO的总线宽度

CPU_SEL; 配置ARM chip ID

UCLK; 配置USB clock (见芯片手册214页)

XTAL_SEL; 配置晶振频率

FCLK; 配置FLCK

CLKDIV_VAL; 设置CLOCK　DIVISION

根据设置CPU_SEL, UCLK, XTAL_SEL, FCLK, CLIKDIV_VAL是用 “if”语句来配置相应的参数如M_MDIV, M_PDIV, M_SDIV, U_MIDV, U_PDIV, U_SDIV

公式如下：Mpll=(2*m*Fin)/(p*2^s)

m=M(the value for divider M)+8, p=P(the value for divider P)+2