全文地址：http://www.cnblogs.com/oomusou/archive/2009/02/14/de2_70_ssram.html
Abstract
一直有人反應無法在DE2-70使用SSRAM，主要是top module接法的錯誤，本文提出解決方法。
Introduction
使用環境：Quartus II 8.1 + Nios II 8.1 EDS + DE2-70 (Cyclone II EP2C70F896C6N)
在帶助教時，就有同學提出無法在DE2-70使用SSRAM的問題，無論是將軟體跑在SSRAM，或是在SSRAM建立一個變數或array都不行，lishyhan學長也曾問我這個問題。
在DE2-70 CD的範例中，DE2_70_NET、DE2_70_NIOS_DEVICE_LED、DE2_70_NIOS_HOST_MOUSE_VGA的top module，SSRAM的接法皆為
// the_tristate_bridge_1_avalon_slave (ssram)
.address_to_the_ssram({oSRAM_A[17:0],SRAM_DUMMY_ADDR}),
.adsc_n_to_the_ssram(oSRAM_ADSC_N),
.bw_n_to_the_ssram(oSRAM_BE_N),
.bwe_n_to_the_ssram(oSRAM_WE_N),
.chipenable1_n_to_the_ssram(oSRAM_CE1_N),
.data_to_and_from_the_ssram((SRAM_DQ)),
.outputenable_n_to_the_ssram(oSRAM_OE_N),
.address_to_the_ssram({oSRAM_A[17:0],SRAM_DUMMY_ADDR}),
.adsc_n_to_the_ssram(oSRAM_ADSC_N),
.bw_n_to_the_ssram(oSRAM_BE_N),
.bwe_n_to_the_ssram(oSRAM_WE_N),
.chipenable1_n_to_the_ssram(oSRAM_CE1_N),
.data_to_and_from_the_ssram((SRAM_DQ)),
.outputenable_n_to_the_ssram(oSRAM_OE_N),
所以在(原創) 如何以32 bit的方式存取SDRAM? (SOC) (Nios II) (SOPC Builder) (DE2-70)這一篇中，我也是依照DE2-70 CD的範例連接SSRAM，core_duo提出了SRAM_A[17..0]和原理图上[18..0]19根地址不符的疑問，若軟體很小，如Hello World，這種寫法仍可正常執行，但若大一點的軟體，如DE2_70_SD_Card_Audio_Player，就會發現無法跑在SSRAM。
正確應該改成如下的寫法，就可完全正常使用SSRAM了。
wire [1:0] sram_dummy_addr; // used to ignore the a0/a1 pin from cypress ssram ip core
.address_to_the_ssram({oSRAM_A[18:0],sram_dummy_addr}), // sram address bus 21 bits
.adsc_n_to_the_ssram(oSRAM_ADSC_N), // sram controller address status
.bw_n_to_the_ssram(oSRAM_BE_N), // sram byte write enable
.bwe_n_to_the_ssram(oSRAM_WE_N), // sram write enable
.chipenable1_n_to_the_ssram(oSRAM_CE1_N), // sram chip enable
.data_to_and_from_the_ssram((SRAM_DQ)), // sram data bus 32 bits
.outputenable_n_to_the_ssram(oSRAM_OE_N), // sram output enable
.address_to_the_ssram({oSRAM_A[18:0],sram_dummy_addr}), // sram address bus 21 bits
.adsc_n_to_the_ssram(oSRAM_ADSC_N), // sram controller address status
.bw_n_to_the_ssram(oSRAM_BE_N), // sram byte write enable
.bwe_n_to_the_ssram(oSRAM_WE_N), // sram write enable
.chipenable1_n_to_the_ssram(oSRAM_CE1_N), // sram chip enable
.data_to_and_from_the_ssram((SRAM_DQ)), // sram data bus 32 bits
.outputenable_n_to_the_ssram(oSRAM_OE_N), // sram output enable
完整的top module如下所示。
DE2_70_NIOS.v / Verilog
1 /*
2 (C) OOMusou 2009 http://oomusou.cnblogs.com
3
4 Filename : DE2_70_NIOS.v
5 Compiler : Quartus II 8.1 + Nios II 8.1
6 Description : DE2_70_NIOS reference design 1.4
7 Release : 02/14/2009 1.0
8 */
9
10 module DE2_70_NIOS (
11 input iCLK_28, // 28.63636 MHz
12 input iCLK_50, // 50 MHz
13 input iCLK_50_2, // 50 MHz
14 input iCLK_50_3, // 50 MHz
15 input iCLK_50_4, // 50 MHz
16 input iEXT_CLOCK, // External Clock
17 ////////////////////////////// Push Button ////////////////////////
18 input [3:0] iKEY, // Pushbutton[3:0]
19 ////////////////////////////// DPDT Switch ////////////////////////
20 input [17:0] iSW, // Toggle Switch[17:0]
21 ////////////////////////////// 7-SEG Dispaly ////////////////////////
22 output [6:0] oHEX0_D, // Seven Segment Digit 0
23 output oHEX0_DP, // Seven Segment Digit 0 decimal point
24 output [6:0] oHEX1_D, // Seven Segment Digit 1
25 output oHEX1_DP, // Seven Segment Digit 1 decimal point
26 output [6:0] oHEX2_D, // Seven Segment Digit 2
27 output oHEX2_DP, // Seven Segment Digit 2 decimal point
28 output [6:0] oHEX3_D, // Seven Segment Digit 3
29 output oHEX3_DP, // Seven Segment Digit 3 decimal point
30 output [6:0] oHEX4_D, // Seven Segment Digit 4
31 output oHEX4_DP, // Seven Segment Digit 4 decimal point
32 output [6:0] oHEX5_D, // Seven Segment Digit 5
33 output oHEX5_DP, // Seven Segment Digit 5 decimal point
34 output [6:0] oHEX6_D, // Seven Segment Digit 6
35 output oHEX6_DP, // Seven Segment Digit 6 decimal point
36 output [6:0] oHEX7_D, // Seven Segment Digit 7
37 output oHEX7_DP, // Seven Segment Digit 7 decimal point
38 //////////////////////////////// LED ////////////////////////////
39 output [8:0] oLEDG, // LED Green[8:0]
40 output [17:0] oLEDR, // LED Red[17:0]
41 //////////////////////////////// UART ////////////////////////////
42 output oUART_TXD, // UART Transmitter
43 input iUART_RXD, // UART Receiver
44 output oUART_CTS, // UART Clear To Send
45 input iUART_RTS, // UART Requst To Send
46 //////////////////////////////// IRDA ////////////////////////////
47 output oIRDA_TXD, // IRDA Transmitter
48 input iIRDA_RXD, // IRDA Receiver
49 //////////////////////////////// SDRAM Interface ////////////////////////
50 inout [31:0] DRAM_DQ, // SDRAM Data bus 32 Bits
51 output [12:0] oDRAM0_A, // SDRAM0 Address bus 12 Bits
52 output [12:0] oDRAM1_A, // SDRAM1 Address bus 12 Bits
53 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
54 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
55 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
56 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
57 output oDRAM0_WE_N, // SDRAM0 Write Enable
58 output oDRAM1_WE_N, // SDRAM1 Write Enable
59 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
60 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
61 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
62 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
63 output oDRAM0_CS_N, // SDRAM0 Chip Select
64 output oDRAM1_CS_N, // SDRAM1 Chip Select
65 output [1:0] oDRAM0_BA, // SDRAM0 Bank Address
66 output [1:0] oDRAM1_BA, // SDRAM1 Bank Address
67 output oDRAM0_CLK, // SDRAM0 Clock
68 output oDRAM1_CLK, // SDRAM0 Clock
69 output oDRAM0_CKE, // SDRAM0 Clock Enable
70 output oDRAM1_CKE, // SDRAM1 Clock Enable
71 //////////////////////////////// Flash Interface ////////////////////////
72 inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
73 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
74 output [25:0] oFLASH_A, // FLASH Address bus 26 Bits
75 output oFLASH_WE_N, // FLASH Write Enable
76 output oFLASH_RST_N, // FLASH Reset
77 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
78 input iFLASH_RY_N, // FLASH Ready/Busy output
79 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
80 output oFLASH_OE_N, // FLASH Output Enable
81 output oFLASH_CE_N, // FLASH Chip Enable
82 //////////////////////////////// SRAM Interface ////////////////////////
83 inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
84 inout [3:0] SRAM_DPA, // SRAM Parity Data Bus
85 output [20:0] oSRAM_A, // SRAM Address bus 21 Bits
86 output oSRAM_ADSC_N, // RAM Controller Address Status
87 output oSRAM_ADSP_N, // SRAM Processor Address Status
88 output oSRAM_ADV_N, // SRAM Burst Address Advance
89 output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
90 output oSRAM_CE1_N, // SRAM Chip Enable
91 output oSRAM_CE2, // SRAM Chip Enable
92 output oSRAM_CE3_N, // SRAM Chip Enable
93 output oSRAM_CLK, // SRAM Clock
94 output oSRAM_GW_N, // SRAM Global Write Enable
95 output oSRAM_OE_N, // SRAM Output Enable
96 output oSRAM_WE_N, // SRAM Write Enable
97 //////////////////////////////// ISP1362 Interface ////////////////////////
98 inout [15:0] OTG_D, // ISP1362 Data bus 16 Bits
99 output [1:0] oOTG_A, // ISP1362 Address 2 Bits
100 output oOTG_CS_N, // ISP1362 Chip Select
101 output oOTG_OE_N, // ISP1362 Read
102 output oOTG_WE_N, // ISP1362 Write
103 output oOTG_RESET_N, // ISP1362 Reset
104 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
105 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
106 input iOTG_INT0, // ISP1362 Interrupt 0
107 input iOTG_INT1, // ISP1362 Interrupt 1
108 input iOTG_DREQ0, // ISP1362 DMA Request 0
109 input iOTG_DREQ1, // ISP1362 DMA Request 1
110 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
111 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
112 //////////////////////////////// LCD Module 16X2 ////////////////////////////
113 inout [7:0] LCD_D, // LCD Data bus 8 bits
114 output oLCD_ON, // LCD Power ON/OFF
115 output oLCD_BLON, // LCD Back Light ON/OFF
116 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
117 output oLCD_EN, // LCD Enable
118 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
119 //////////////////////////////// SD Card Interface ////////////////////////
120 inout SD_DAT, // SD Card Data
121 inout SD_DAT3, // SD Card Data 3
122 inout SD_CMD, // SD Card Command Signal
123 output oSD_CLK, // SD Card Clock
124 //////////////////////////////// I2C ////////////////////////////////
125 inout I2C_SDAT, // I2C Data
126 output oI2C_SCLK, // I2C Clock
127 //////////////////////////////// PS2 ////////////////////////////
128 inout PS2_KBDAT, // PS2 Keyboard Data
129 inout PS2_KBCLK, // PS2 Keyboard Clock
130 inout PS2_MSDAT, // PS2 Mouse Data
131 inout PS2_MSCLK, // PS2 Mouse Clock
132 //////////////////////////////// VGA ////////////////////////////
133 output oVGA_CLOCK, // VGA Clock
134 output oVGA_HS, // VGA H_SYNC
135 output oVGA_VS, // VGA V_SYNC
136 output oVGA_BLANK_N, // VGA BLANK
137 output oVGA_SYNC_N, // VGA SYNC
138 output [9:0] oVGA_R, // VGA Red[9:0]
139 output [9:0] oVGA_G, // VGA Green[9:0]
140 output [9:0] oVGA_B, // VGA Blue[9:0]
141 //////////////////////////////// Ethernet Interface ////////////////////////////
142 inout [15:0] ENET_D, // DM9000A DATA bus 16Bits
143 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
144 output oENET_CS_N, // DM9000A Chip Select
145 output oENET_IOW_N, // DM9000A Write
146 output oENET_IOR_N, // DM9000A Read
147 output oENET_RESET_N, // DM9000A Reset
148 input iENET_INT, // DM9000A Interrupt
149 output oENET_CLK, // DM9000A Clock 25 MHz
150 //////////////////////////////// Audio CODEC ////////////////////////////
151 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
152 input iAUD_ADCDAT, // Audio CODEC ADC Data
153 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
154 output oAUD_DACDAT, // Audio CODEC DAC Data
155 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
156 output oAUD_XCK, // Audio CODEC Chip Clock
157 //////////////////////////////// TV Devoder ////////////////////////////
158 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
159 input [7:0] iTD1_D, // TV Decoder1 Data bus 8 bits
160 input iTD1_HS, // TV Decoder1 H_SYNC
161 input iTD1_VS, // TV Decoder1 V_SYNC
162 output oTD1_RESET_N, // TV Decoder1 Reset
163 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
164 input [7:0] iTD2_D, // TV Decoder2 Data bus 8 bits
165 input iTD2_HS, // TV Decoder2 H_SYNC
166 input iTD2_VS, // TV Decoder2 V_SYNC
167 output oTD2_RESET_N, // TV Decoder2 Reset
168 //////////////////////////////// GPIO ////////////////////////////////
169 inout [31:0] GPIO_0, // GPIO Connection 0 I/O
170 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
171 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
172 output GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
173 output GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
174 inout [31:0] GPIO_1, // GPIO Connection 1 I/O
175 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
176 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
177 output GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
178 output GPIO_CLKOUT_P1 // PIO Connection 1 Clock Output 1
179 );
180
181 // All inout port turn to tri-state
182 assign SD_DAT = 1'bz;
183 assign GPIO_0 = 32'hzzzzzzzzz;
184 assign GPIO_1 = 32'hzzzzzzzzz;
185 assign AUD_ADCLRCK = 1'bz;
186
187 // Turn On TV Decoder
188 assign oTD1_RESET_N = 1'bz;
189 assign oTD2_RESET_N = 1'bz;
190
191 // Flash
192 assign FL_RST_N = 1'b1;
193
194 // 16*2 LCD Module
195 assign oLCD_ON = 1'b1; // LCD ON
196 assign oLCD_BLON = 1'b1; // LCD Back Light
197
198 // Disable USB speed select
199 assign OTG_FSPEED = 1'bz;
200 assign OTG_LSPEED = 1'bz;
201
202 // FLASH
203 wire FLASH_16BIT_IP_A0;
204 assign oFLASH_BYTE_N = 1'b1; // FLASH Byte/Word Mode Configuration
205 assign oFLASH_RST_N = 1'b1; // FLASH Reset
206 assign oFLASH_WP_N = 1'b1; // FLASH Write Protect /Programming Acceleration
207
208 // ssram
209 wire sram_clk; // sram clock
210 wire [1:0] sram_dummy_addr; // used to ignore the a0/a1 pin from cypress ssram ip core
211 wire sram_dummy_addr0; // used to ignore msb of sram address
212
213
214 assign oSRAM_ADSP_N = 1'b1; // SRAM Processor Address Status
215 assign oSRAM_ADV_N = 1'b1; // SRAM Burst Address Advance
216 assign oSRAM_CE2 = ~oSRAM_CE1_N; // SRAM Chip Enable
217 assign oSRAM_CE3_N = oSRAM_CE1_N; // SRAM Chip Enable
218 assign oSRAM_GW_N = 1'b1; // SRAM Global Write Enable
219 assign oSRAM_CLK = SRAM_CLK;
220
221 // SDRAM
222 // the sdram is shahred with rtl and nios
223 wire [12:0] dram_a;
224 wire [1:0] dram_ba;
225 wire dram_cas_n;
226 wire dram_cke;
227 wire dram_cs_n;
228 wire [3:0] dram_dqm;
229 wire dram_ras_n;
230 wire dram_we_n;
231
232 // dram1
233 assign oDRAM0_CLK = SRAM_CLK; // SDRAM0 Clock
234 assign oDRAM1_CLK = SRAM_CLK; // SDRAM1 Clock
235
236 assign oDRAM0_A = dram_a;
237 assign oDRAM0_BA = dram_ba;
238 assign oDRAM0_CAS_N = dram_cas_n;
239 assign oDRAM0_CKE = dram_cke;
240 assign oDRAM0_CS_N = dram_cs_n;
241 assign oDRAM0_LDQM0 = dram_dqm[0];
242 assign oDRAM0_UDQM1 = dram_dqm[1];
243 assign oDRAM0_RAS_N = dram_ras_n;
244 assign oDRAM0_WE_N = dram_we_n;
245
246 // dram2
247 assign oDRAM1_A = dram_a;
248 assign oDRAM1_BA = dram_ba;
249 assign oDRAM1_CAS_N = dram_cas_n;
250 assign oDRAM1_CKE = dram_cke;
251 assign oDRAM1_CS_N = dram_cs_n;
252 assign oDRAM1_LDQM0 = dram_dqm[2];
253 assign oDRAM1_UDQM1 = dram_dqm[3];
254 assign oDRAM1_RAS_N = dram_ras_n;
255 assign oDRAM1_WE_N = dram_we_n;
256
257 // USB
258 assign OTG_FSPEED = 1'bz; // USB Full Speed, 0 = Enable, Z = Disable
259 assign OTG_LSPEED = 1'bz; // USB Low Speed, 0 = Enable, Z = Disable
260
261 // Clock 25MHz
262 reg iCLK_25;
263
264 always@(posedge iCLK_50)
265 iCLK_25 <= ~iCLK_25;
266
267 // NIOS CPU
268 wire CPU_CLK;
269 wire CPU_RESET_N;
270
271 Reset_Delay delay0 (
272 .iRST(iKEY[0]),
273 .iCLK(iCLK_50),
274 .oRESET(CPU_RESET_N)
275 );
276
277 // NIOS II system
278 nios_ii nios_ii0 (
279 // 1) global signals:
280 .clk_50(iCLK_50),
281 .pll_c0_system(CPU_CLK),
282 .pll_c1_memory(SRAM_CLK),
283 .pll_c2_audio(oAUD_XCK),
284 .reset_n(CPU_RESET_N),
285 .clk_25(iCLK_25),
286 // the_DM9000A_IF_0
287 .avs_s1_export_ENET_CLK_from_the_DM9000A(oENET_CLK),
288 .avs_s1_export_ENET_CMD_from_the_DM9000A(oENET_CMD),
289 .avs_s1_export_ENET_CS_N_from_the_DM9000A(oENET_CS_N),
290 .avs_s1_export_ENET_DATA_to_and_from_the_DM9000A(ENET_D),
291 .avs_s1_export_ENET_INT_to_the_DM9000A(iENET_INT),
292 .avs_s1_export_ENET_RD_N_from_the_DM9000A(oENET_IOR_N),
293 .avs_s1_export_ENET_RST_N_from_the_DM9000A(oENET_RESET_N),
294 .avs_s1_export_ENET_WR_N_from_the_DM9000A(oENET_IOW_N),
295 // the_ISP1362
296 .avs_hc_export_OTG_ADDR_from_the_ISP1362(oOTG_A),
297 .avs_hc_export_OTG_CS_N_from_the_ISP1362(oOTG_CS_N),
298 .avs_hc_export_OTG_DATA_to_and_from_the_ISP1362(OTG_D),
299 .avs_hc_export_OTG_INT0_to_the_ISP1362(iOTG_INT0),
300 .avs_hc_export_OTG_RD_N_from_the_ISP1362(oOTG_OE_N),
301 .avs_hc_export_OTG_RST_N_from_the_ISP1362(oOTG_RESET_N),
302 .avs_hc_export_OTG_WR_N_from_the_ISP1362(oOTG_WE_N),
303 .avs_dc_export_OTG_INT1_to_the_ISP1362(iOTG_INT1),
304 // the_audio
305 .avs_s1_export_BCLK_to_the_AUDIO(AUD_BCLK),
306 .avs_s1_export_DACLRC_to_the_AUDIO(AUD_DACLRCK),
307 .avs_s1_export_DACDAT_from_the_AUDIO(oAUD_DACDAT),
308 .avs_s1_export_ADCLRC_to_the_AUDIO(AUD_ADCLRCK),
309 .avs_s1_export_ADCDAT_to_the_AUDIO(iAUD_ADCDAT),
310 // the_i2c_sclk
311 .out_port_from_the_i2c_sclk(oI2C_SCLK),
312 // the_i2c_sdat
313 .bidir_port_to_and_from_the_i2c_sdat(I2C_SDAT),
314 // the_lcd
315 .LCD_E_from_the_lcd(oLCD_EN),
316 .LCD_RS_from_the_lcd(oLCD_RS),
317 .LCD_RW_from_the_lcd(oLCD_RW),
318 .LCD_data_to_and_from_the_lcd(LCD_D),
319 // the_pio_button
320 .in_port_to_the_pio_button(iKEY),
321 // the_pio_green_led
322 .out_port_from_the_pio_green_led(oLEDG),
323 // the_pio_red_led
324 .out_port_from_the_pio_red_led(oLEDR),
325 // the_seg7
326 .avs_s1_export_seg7_from_the_SEG7({oHEX7_DP, oHEX7_D, oHEX6_DP, oHEX6_D, oHEX5_DP,
327 oHEX5_D, oHEX4_DP,oHEX4_D, oHEX3_DP, oHEX3_D, oHEX2_DP, oHEX2_D, oHEX1_DP, oHEX1_D,
328 oHEX0_DP, oHEX0_D}),
329 // the_pio_switch
330 .in_port_to_the_pio_switch(iSW),
331 // the_sd_clk
332 .out_port_from_the_sd_clk(oSD_CLK),
333 // the_sd_cmd
334 .bidir_port_to_and_from_the_sd_cmd(SD_CMD),
335 // the_sd_dat
336 .bidir_port_to_and_from_the_sd_dat(SD_DAT),
337 // the_sd_dat3
338 .bidir_port_to_and_from_the_sd_dat3(SD_DAT3),
339 // the_sdram (u1)
340 .zs_addr_from_the_sdram(dram_a),
341 .zs_ba_from_the_sdram(dram_ba),
342 .zs_cas_n_from_the_sdram(dram_cas_n),
343 .zs_cke_from_the_sdram(dram_cke),
344 .zs_cs_n_from_the_sdram(dram_cs_n),
345 .zs_dq_to_and_from_the_sdram(DRAM_DQ),
346 .zs_dqm_from_the_sdram(dram_dqm),
347 .zs_ras_n_from_the_sdram(dram_ras_n),
348 .zs_we_n_from_the_sdram(dram_we_n),
349 // the_tristate_bridge_avalon_slave (flash)
350 .address_to_the_cfi_flash({oFLASH_A[21:0],FLASH_16BIT_IP_A0}),
351 .data_to_and_from_the_cfi_flash({FLASH_DQ15_AM1,FLASH_DQ}),
352 .read_n_to_the_cfi_flash(oFLASH_OE_N),
353 .select_n_to_the_cfi_flash(oFLASH_CE_N),
354 .write_n_to_the_cfi_flash(oFLASH_WE_N),
355 .address_to_the_ssram({oSRAM_A[18:0],sram_dummy_addr}), // sram address bus 21 bits
356 .adsc_n_to_the_ssram(oSRAM_ADSC_N), // sram controller address status
357 .bw_n_to_the_ssram(oSRAM_BE_N), // sram byte write enable
358 .bwe_n_to_the_ssram(oSRAM_WE_N), // sram write enable
359 .chipenable1_n_to_the_ssram(oSRAM_CE1_N), // sram chip enable
360 .data_to_and_from_the_ssram((SRAM_DQ)), // sram data bus 32 bits
361 .outputenable_n_to_the_ssram(oSRAM_OE_N), // sram output enable
362 // the_uart
363 .cts_n_to_the_uart(oUART_CTS),
364 .rts_n_from_the_uart(iUART_RTS),
365 .rxd_to_the_uart(iUART_RXD),
366 .txd_from_the_uart(oUART_TXD),
367 );
368
369 endmodule
2 (C) OOMusou 2009 http://oomusou.cnblogs.com
3
4 Filename : DE2_70_NIOS.v
5 Compiler : Quartus II 8.1 + Nios II 8.1
6 Description : DE2_70_NIOS reference design 1.4
7 Release : 02/14/2009 1.0
8 */
9
10 module DE2_70_NIOS (
11 input iCLK_28, // 28.63636 MHz
12 input iCLK_50, // 50 MHz
13 input iCLK_50_2, // 50 MHz
14 input iCLK_50_3, // 50 MHz
15 input iCLK_50_4, // 50 MHz
16 input iEXT_CLOCK, // External Clock
17 ////////////////////////////// Push Button ////////////////////////
18 input [3:0] iKEY, // Pushbutton[3:0]
19 ////////////////////////////// DPDT Switch ////////////////////////
20 input [17:0] iSW, // Toggle Switch[17:0]
21 ////////////////////////////// 7-SEG Dispaly ////////////////////////
22 output [6:0] oHEX0_D, // Seven Segment Digit 0
23 output oHEX0_DP, // Seven Segment Digit 0 decimal point
24 output [6:0] oHEX1_D, // Seven Segment Digit 1
25 output oHEX1_DP, // Seven Segment Digit 1 decimal point
26 output [6:0] oHEX2_D, // Seven Segment Digit 2
27 output oHEX2_DP, // Seven Segment Digit 2 decimal point
28 output [6:0] oHEX3_D, // Seven Segment Digit 3
29 output oHEX3_DP, // Seven Segment Digit 3 decimal point
30 output [6:0] oHEX4_D, // Seven Segment Digit 4
31 output oHEX4_DP, // Seven Segment Digit 4 decimal point
32 output [6:0] oHEX5_D, // Seven Segment Digit 5
33 output oHEX5_DP, // Seven Segment Digit 5 decimal point
34 output [6:0] oHEX6_D, // Seven Segment Digit 6
35 output oHEX6_DP, // Seven Segment Digit 6 decimal point
36 output [6:0] oHEX7_D, // Seven Segment Digit 7
37 output oHEX7_DP, // Seven Segment Digit 7 decimal point
38 //////////////////////////////// LED ////////////////////////////
39 output [8:0] oLEDG, // LED Green[8:0]
40 output [17:0] oLEDR, // LED Red[17:0]
41 //////////////////////////////// UART ////////////////////////////
42 output oUART_TXD, // UART Transmitter
43 input iUART_RXD, // UART Receiver
44 output oUART_CTS, // UART Clear To Send
45 input iUART_RTS, // UART Requst To Send
46 //////////////////////////////// IRDA ////////////////////////////
47 output oIRDA_TXD, // IRDA Transmitter
48 input iIRDA_RXD, // IRDA Receiver
49 //////////////////////////////// SDRAM Interface ////////////////////////
50 inout [31:0] DRAM_DQ, // SDRAM Data bus 32 Bits
51 output [12:0] oDRAM0_A, // SDRAM0 Address bus 12 Bits
52 output [12:0] oDRAM1_A, // SDRAM1 Address bus 12 Bits
53 output oDRAM0_LDQM0, // SDRAM0 Low-byte Data Mask
54 output oDRAM1_LDQM0, // SDRAM1 Low-byte Data Mask
55 output oDRAM0_UDQM1, // SDRAM0 High-byte Data Mask
56 output oDRAM1_UDQM1, // SDRAM1 High-byte Data Mask
57 output oDRAM0_WE_N, // SDRAM0 Write Enable
58 output oDRAM1_WE_N, // SDRAM1 Write Enable
59 output oDRAM0_CAS_N, // SDRAM0 Column Address Strobe
60 output oDRAM1_CAS_N, // SDRAM1 Column Address Strobe
61 output oDRAM0_RAS_N, // SDRAM0 Row Address Strobe
62 output oDRAM1_RAS_N, // SDRAM1 Row Address Strobe
63 output oDRAM0_CS_N, // SDRAM0 Chip Select
64 output oDRAM1_CS_N, // SDRAM1 Chip Select
65 output [1:0] oDRAM0_BA, // SDRAM0 Bank Address
66 output [1:0] oDRAM1_BA, // SDRAM1 Bank Address
67 output oDRAM0_CLK, // SDRAM0 Clock
68 output oDRAM1_CLK, // SDRAM0 Clock
69 output oDRAM0_CKE, // SDRAM0 Clock Enable
70 output oDRAM1_CKE, // SDRAM1 Clock Enable
71 //////////////////////////////// Flash Interface ////////////////////////
72 inout [14:0] FLASH_DQ, // FLASH Data bus 15 Bits (0 to 14)
73 inout FLASH_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1
74 output [25:0] oFLASH_A, // FLASH Address bus 26 Bits
75 output oFLASH_WE_N, // FLASH Write Enable
76 output oFLASH_RST_N, // FLASH Reset
77 output oFLASH_WP_N, // FLASH Write Protect /Programming Acceleration
78 input iFLASH_RY_N, // FLASH Ready/Busy output
79 output oFLASH_BYTE_N, // FLASH Byte/Word Mode Configuration
80 output oFLASH_OE_N, // FLASH Output Enable
81 output oFLASH_CE_N, // FLASH Chip Enable
82 //////////////////////////////// SRAM Interface ////////////////////////
83 inout [31:0] SRAM_DQ, // SRAM Data Bus 32 Bits
84 inout [3:0] SRAM_DPA, // SRAM Parity Data Bus
85 output [20:0] oSRAM_A, // SRAM Address bus 21 Bits
86 output oSRAM_ADSC_N, // RAM Controller Address Status
87 output oSRAM_ADSP_N, // SRAM Processor Address Status
88 output oSRAM_ADV_N, // SRAM Burst Address Advance
89 output [3:0] oSRAM_BE_N, // SRAM Byte Write Enable
90 output oSRAM_CE1_N, // SRAM Chip Enable
91 output oSRAM_CE2, // SRAM Chip Enable
92 output oSRAM_CE3_N, // SRAM Chip Enable
93 output oSRAM_CLK, // SRAM Clock
94 output oSRAM_GW_N, // SRAM Global Write Enable
95 output oSRAM_OE_N, // SRAM Output Enable
96 output oSRAM_WE_N, // SRAM Write Enable
97 //////////////////////////////// ISP1362 Interface ////////////////////////
98 inout [15:0] OTG_D, // ISP1362 Data bus 16 Bits
99 output [1:0] oOTG_A, // ISP1362 Address 2 Bits
100 output oOTG_CS_N, // ISP1362 Chip Select
101 output oOTG_OE_N, // ISP1362 Read
102 output oOTG_WE_N, // ISP1362 Write
103 output oOTG_RESET_N, // ISP1362 Reset
104 inout OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
105 inout OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
106 input iOTG_INT0, // ISP1362 Interrupt 0
107 input iOTG_INT1, // ISP1362 Interrupt 1
108 input iOTG_DREQ0, // ISP1362 DMA Request 0
109 input iOTG_DREQ1, // ISP1362 DMA Request 1
110 output oOTG_DACK0_N, // ISP1362 DMA Acknowledge 0
111 output oOTG_DACK1_N, // ISP1362 DMA Acknowledge 1
112 //////////////////////////////// LCD Module 16X2 ////////////////////////////
113 inout [7:0] LCD_D, // LCD Data bus 8 bits
114 output oLCD_ON, // LCD Power ON/OFF
115 output oLCD_BLON, // LCD Back Light ON/OFF
116 output oLCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
117 output oLCD_EN, // LCD Enable
118 output oLCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
119 //////////////////////////////// SD Card Interface ////////////////////////
120 inout SD_DAT, // SD Card Data
121 inout SD_DAT3, // SD Card Data 3
122 inout SD_CMD, // SD Card Command Signal
123 output oSD_CLK, // SD Card Clock
124 //////////////////////////////// I2C ////////////////////////////////
125 inout I2C_SDAT, // I2C Data
126 output oI2C_SCLK, // I2C Clock
127 //////////////////////////////// PS2 ////////////////////////////
128 inout PS2_KBDAT, // PS2 Keyboard Data
129 inout PS2_KBCLK, // PS2 Keyboard Clock
130 inout PS2_MSDAT, // PS2 Mouse Data
131 inout PS2_MSCLK, // PS2 Mouse Clock
132 //////////////////////////////// VGA ////////////////////////////
133 output oVGA_CLOCK, // VGA Clock
134 output oVGA_HS, // VGA H_SYNC
135 output oVGA_VS, // VGA V_SYNC
136 output oVGA_BLANK_N, // VGA BLANK
137 output oVGA_SYNC_N, // VGA SYNC
138 output [9:0] oVGA_R, // VGA Red[9:0]
139 output [9:0] oVGA_G, // VGA Green[9:0]
140 output [9:0] oVGA_B, // VGA Blue[9:0]
141 //////////////////////////////// Ethernet Interface ////////////////////////////
142 inout [15:0] ENET_D, // DM9000A DATA bus 16Bits
143 output oENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
144 output oENET_CS_N, // DM9000A Chip Select
145 output oENET_IOW_N, // DM9000A Write
146 output oENET_IOR_N, // DM9000A Read
147 output oENET_RESET_N, // DM9000A Reset
148 input iENET_INT, // DM9000A Interrupt
149 output oENET_CLK, // DM9000A Clock 25 MHz
150 //////////////////////////////// Audio CODEC ////////////////////////////
151 inout AUD_ADCLRCK, // Audio CODEC ADC LR Clock
152 input iAUD_ADCDAT, // Audio CODEC ADC Data
153 inout AUD_DACLRCK, // Audio CODEC DAC LR Clock
154 output oAUD_DACDAT, // Audio CODEC DAC Data
155 inout AUD_BCLK, // Audio CODEC Bit-Stream Clock
156 output oAUD_XCK, // Audio CODEC Chip Clock
157 //////////////////////////////// TV Devoder ////////////////////////////
158 input iTD1_CLK27, // TV Decoder1 Line_Lock Output Clock
159 input [7:0] iTD1_D, // TV Decoder1 Data bus 8 bits
160 input iTD1_HS, // TV Decoder1 H_SYNC
161 input iTD1_VS, // TV Decoder1 V_SYNC
162 output oTD1_RESET_N, // TV Decoder1 Reset
163 input iTD2_CLK27, // TV Decoder2 Line_Lock Output Clock
164 input [7:0] iTD2_D, // TV Decoder2 Data bus 8 bits
165 input iTD2_HS, // TV Decoder2 H_SYNC
166 input iTD2_VS, // TV Decoder2 V_SYNC
167 output oTD2_RESET_N, // TV Decoder2 Reset
168 //////////////////////////////// GPIO ////////////////////////////////
169 inout [31:0] GPIO_0, // GPIO Connection 0 I/O
170 input GPIO_CLKIN_N0, // GPIO Connection 0 Clock Input 0
171 input GPIO_CLKIN_P0, // GPIO Connection 0 Clock Input 1
172 output GPIO_CLKOUT_N0, // GPIO Connection 0 Clock Output 0
173 output GPIO_CLKOUT_P0, // GPIO Connection 0 Clock Output 1
174 inout [31:0] GPIO_1, // GPIO Connection 1 I/O
175 input GPIO_CLKIN_N1, // GPIO Connection 1 Clock Input 0
176 input GPIO_CLKIN_P1, // GPIO Connection 1 Clock Input 1
177 output GPIO_CLKOUT_N1, // GPIO Connection 1 Clock Output 0
178 output GPIO_CLKOUT_P1 // PIO Connection 1 Clock Output 1
179 );
180
181 // All inout port turn to tri-state
182 assign SD_DAT = 1'bz;
183 assign GPIO_0 = 32'hzzzzzzzzz;
184 assign GPIO_1 = 32'hzzzzzzzzz;
185 assign AUD_ADCLRCK = 1'bz;
186
187 // Turn On TV Decoder
188 assign oTD1_RESET_N = 1'bz;
189 assign oTD2_RESET_N = 1'bz;
190
191 // Flash
192 assign FL_RST_N = 1'b1;
193
194 // 16*2 LCD Module
195 assign oLCD_ON = 1'b1; // LCD ON
196 assign oLCD_BLON = 1'b1; // LCD Back Light
197
198 // Disable USB speed select
199 assign OTG_FSPEED = 1'bz;
200 assign OTG_LSPEED = 1'bz;
201
202 // FLASH
203 wire FLASH_16BIT_IP_A0;
204 assign oFLASH_BYTE_N = 1'b1; // FLASH Byte/Word Mode Configuration
205 assign oFLASH_RST_N = 1'b1; // FLASH Reset
206 assign oFLASH_WP_N = 1'b1; // FLASH Write Protect /Programming Acceleration
207
208 // ssram
209 wire sram_clk; // sram clock
210 wire [1:0] sram_dummy_addr; // used to ignore the a0/a1 pin from cypress ssram ip core
211 wire sram_dummy_addr0; // used to ignore msb of sram address
212
213
214 assign oSRAM_ADSP_N = 1'b1; // SRAM Processor Address Status
215 assign oSRAM_ADV_N = 1'b1; // SRAM Burst Address Advance
216 assign oSRAM_CE2 = ~oSRAM_CE1_N; // SRAM Chip Enable
217 assign oSRAM_CE3_N = oSRAM_CE1_N; // SRAM Chip Enable
218 assign oSRAM_GW_N = 1'b1; // SRAM Global Write Enable
219 assign oSRAM_CLK = SRAM_CLK;
220
221 // SDRAM
222 // the sdram is shahred with rtl and nios
223 wire [12:0] dram_a;
224 wire [1:0] dram_ba;
225 wire dram_cas_n;
226 wire dram_cke;
227 wire dram_cs_n;
228 wire [3:0] dram_dqm;
229 wire dram_ras_n;
230 wire dram_we_n;
231
232 // dram1
233 assign oDRAM0_CLK = SRAM_CLK; // SDRAM0 Clock
234 assign oDRAM1_CLK = SRAM_CLK; // SDRAM1 Clock
235
236 assign oDRAM0_A = dram_a;
237 assign oDRAM0_BA = dram_ba;
238 assign oDRAM0_CAS_N = dram_cas_n;
239 assign oDRAM0_CKE = dram_cke;
240 assign oDRAM0_CS_N = dram_cs_n;
241 assign oDRAM0_LDQM0 = dram_dqm[0];
242 assign oDRAM0_UDQM1 = dram_dqm[1];
243 assign oDRAM0_RAS_N = dram_ras_n;
244 assign oDRAM0_WE_N = dram_we_n;
245
246 // dram2
247 assign oDRAM1_A = dram_a;
248 assign oDRAM1_BA = dram_ba;
249 assign oDRAM1_CAS_N = dram_cas_n;
250 assign oDRAM1_CKE = dram_cke;
251 assign oDRAM1_CS_N = dram_cs_n;
252 assign oDRAM1_LDQM0 = dram_dqm[2];
253 assign oDRAM1_UDQM1 = dram_dqm[3];
254 assign oDRAM1_RAS_N = dram_ras_n;
255 assign oDRAM1_WE_N = dram_we_n;
256
257 // USB
258 assign OTG_FSPEED = 1'bz; // USB Full Speed, 0 = Enable, Z = Disable
259 assign OTG_LSPEED = 1'bz; // USB Low Speed, 0 = Enable, Z = Disable
260
261 // Clock 25MHz
262 reg iCLK_25;
263
264 always@(posedge iCLK_50)
265 iCLK_25 <= ~iCLK_25;
266
267 // NIOS CPU
268 wire CPU_CLK;
269 wire CPU_RESET_N;
270
271 Reset_Delay delay0 (
272 .iRST(iKEY[0]),
273 .iCLK(iCLK_50),
274 .oRESET(CPU_RESET_N)
275 );
276
277 // NIOS II system
278 nios_ii nios_ii0 (
279 // 1) global signals:
280 .clk_50(iCLK_50),
281 .pll_c0_system(CPU_CLK),
282 .pll_c1_memory(SRAM_CLK),
283 .pll_c2_audio(oAUD_XCK),
284 .reset_n(CPU_RESET_N),
285 .clk_25(iCLK_25),
286 // the_DM9000A_IF_0
287 .avs_s1_export_ENET_CLK_from_the_DM9000A(oENET_CLK),
288 .avs_s1_export_ENET_CMD_from_the_DM9000A(oENET_CMD),
289 .avs_s1_export_ENET_CS_N_from_the_DM9000A(oENET_CS_N),
290 .avs_s1_export_ENET_DATA_to_and_from_the_DM9000A(ENET_D),
291 .avs_s1_export_ENET_INT_to_the_DM9000A(iENET_INT),
292 .avs_s1_export_ENET_RD_N_from_the_DM9000A(oENET_IOR_N),
293 .avs_s1_export_ENET_RST_N_from_the_DM9000A(oENET_RESET_N),
294 .avs_s1_export_ENET_WR_N_from_the_DM9000A(oENET_IOW_N),
295 // the_ISP1362
296 .avs_hc_export_OTG_ADDR_from_the_ISP1362(oOTG_A),
297 .avs_hc_export_OTG_CS_N_from_the_ISP1362(oOTG_CS_N),
298 .avs_hc_export_OTG_DATA_to_and_from_the_ISP1362(OTG_D),
299 .avs_hc_export_OTG_INT0_to_the_ISP1362(iOTG_INT0),
300 .avs_hc_export_OTG_RD_N_from_the_ISP1362(oOTG_OE_N),
301 .avs_hc_export_OTG_RST_N_from_the_ISP1362(oOTG_RESET_N),
302 .avs_hc_export_OTG_WR_N_from_the_ISP1362(oOTG_WE_N),
303 .avs_dc_export_OTG_INT1_to_the_ISP1362(iOTG_INT1),
304 // the_audio
305 .avs_s1_export_BCLK_to_the_AUDIO(AUD_BCLK),
306 .avs_s1_export_DACLRC_to_the_AUDIO(AUD_DACLRCK),
307 .avs_s1_export_DACDAT_from_the_AUDIO(oAUD_DACDAT),
308 .avs_s1_export_ADCLRC_to_the_AUDIO(AUD_ADCLRCK),
309 .avs_s1_export_ADCDAT_to_the_AUDIO(iAUD_ADCDAT),
310 // the_i2c_sclk
311 .out_port_from_the_i2c_sclk(oI2C_SCLK),
312 // the_i2c_sdat
313 .bidir_port_to_and_from_the_i2c_sdat(I2C_SDAT),
314 // the_lcd
315 .LCD_E_from_the_lcd(oLCD_EN),
316 .LCD_RS_from_the_lcd(oLCD_RS),
317 .LCD_RW_from_the_lcd(oLCD_RW),
318 .LCD_data_to_and_from_the_lcd(LCD_D),
319 // the_pio_button
320 .in_port_to_the_pio_button(iKEY),
321 // the_pio_green_led
322 .out_port_from_the_pio_green_led(oLEDG),
323 // the_pio_red_led
324 .out_port_from_the_pio_red_led(oLEDR),
325 // the_seg7
326 .avs_s1_export_seg7_from_the_SEG7({oHEX7_DP, oHEX7_D, oHEX6_DP, oHEX6_D, oHEX5_DP,
327 oHEX5_D, oHEX4_DP,oHEX4_D, oHEX3_DP, oHEX3_D, oHEX2_DP, oHEX2_D, oHEX1_DP, oHEX1_D,
328 oHEX0_DP, oHEX0_D}),
329 // the_pio_switch
330 .in_port_to_the_pio_switch(iSW),
331 // the_sd_clk
332 .out_port_from_the_sd_clk(oSD_CLK),
333 // the_sd_cmd
334 .bidir_port_to_and_from_the_sd_cmd(SD_CMD),
335 // the_sd_dat
336 .bidir_port_to_and_from_the_sd_dat(SD_DAT),
337 // the_sd_dat3
338 .bidir_port_to_and_from_the_sd_dat3(SD_DAT3),
339 // the_sdram (u1)
340 .zs_addr_from_the_sdram(dram_a),
341 .zs_ba_from_the_sdram(dram_ba),
342 .zs_cas_n_from_the_sdram(dram_cas_n),
343 .zs_cke_from_the_sdram(dram_cke),
344 .zs_cs_n_from_the_sdram(dram_cs_n),
345 .zs_dq_to_and_from_the_sdram(DRAM_DQ),
346 .zs_dqm_from_the_sdram(dram_dqm),
347 .zs_ras_n_from_the_sdram(dram_ras_n),
348 .zs_we_n_from_the_sdram(dram_we_n),
349 // the_tristate_bridge_avalon_slave (flash)
350 .address_to_the_cfi_flash({oFLASH_A[21:0],FLASH_16BIT_IP_A0}),
351 .data_to_and_from_the_cfi_flash({FLASH_DQ15_AM1,FLASH_DQ}),
352 .read_n_to_the_cfi_flash(oFLASH_OE_N),
353 .select_n_to_the_cfi_flash(oFLASH_CE_N),
354 .write_n_to_the_cfi_flash(oFLASH_WE_N),
355 .address_to_the_ssram({oSRAM_A[18:0],sram_dummy_addr}), // sram address bus 21 bits
356 .adsc_n_to_the_ssram(oSRAM_ADSC_N), // sram controller address status
357 .bw_n_to_the_ssram(oSRAM_BE_N), // sram byte write enable
358 .bwe_n_to_the_ssram(oSRAM_WE_N), // sram write enable
359 .chipenable1_n_to_the_ssram(oSRAM_CE1_N), // sram chip enable
360 .data_to_and_from_the_ssram((SRAM_DQ)), // sram data bus 32 bits
361 .outputenable_n_to_the_ssram(oSRAM_OE_N), // sram output enable
362 // the_uart
363 .cts_n_to_the_uart(oUART_CTS),
364 .rts_n_from_the_uart(iUART_RTS),
365 .rxd_to_the_uart(iUART_RXD),
366 .txd_from_the_uart(oUART_TXD),
367 );
368
369 endmodule
完整程式碼下載
DE2_70_NIOS_14_ssram.7z
See Also
(原創) 如何以32 bit的方式存取SDRAM? (SOC) (Nios II) (SOPC Builder) (DE2-70)