【原创】DE2实验解答—lab8 (Quartus) (Digital Logic) (Verilog HDL)

Introduction

    本练习主要研究FPGA片内/外存储器。实现32X8-bit的RAM。

   

Design

 

Part I 用LPM实现RAM

    LPM的用法参阅<Using Library Module in Verilog Design>。

    1. Tools / MegaWizard Plug-in Manger /…/ memory compiles创建一个名为ramlpm.v的RAM。

       

    2. 编译，并查看编译报告。RAM占用1个M4K块，256B。

    3. 仿真。

        仿真结果：

       

 代码part 1:

//part 1 用altsyncram LPM构建一个32*8bit RAM
 
 module part1(
                    input [4:0] Address,
                    input [7:0] DataIn,
                    input Write,Clock,
                    output [7:0] DataOut
                    );
                    
ramlpm u0(
                .address(Address),
                .clock(Clock),
                .data(DataIn),
                .wren(Write),
                .q(DataOut)
                );
                
 endmodule
                    
            

 // megafunction wizard: %RAM: 1-PORT%
 // GENERATION: STANDARD
 // VERSION: WM1.0
 // MODULE: altsyncram 

 // ============================================================
 // File Name: ramlpm.v
 // Megafunction Name(s):
 //             altsyncram
 //
 // Simulation Library Files(s):
 //             altera_mf
 // ============================================================
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ramlpm (
    address,
    clock,
    data,
    wren,
    q);

    input    [4:0]  address;
    input      clock;
    input    [7:0]  data;
    input      wren;
    output    [7:0]  q;

    wire [7:0] sub_wire0;
    wire [7:0] q = sub_wire0[7:0];

    altsyncram    altsyncram_component (
                .wren_a (wren),
                .clock0 (clock),
                .address_a (address),
                .data_a (data),
                .q_a (sub_wire0),
                .aclr0 (1'b0),
                .aclr1 (1'b0),
                .address_b (1'b1),
                .addressstall_a (1'b0),
                .addressstall_b (1'b0),
                .byteena_a (1'b1),
                .byteena_b (1'b1),
                .clock1 (1'b1),
                .clocken0 (1'b1),
                .clocken1 (1'b1),
                .clocken2 (1'b1),
                .clocken3 (1'b1),
                .data_b (1'b1),
                .eccstatus (),
                .q_b (),
                .rden_a (1'b1),
                .rden_b (1'b1),
                .wren_b (1'b0));
    defparam
        altsyncram_component.clock_enable_input_a = "BYPASS",
        altsyncram_component.clock_enable_output_a = "BYPASS",
        altsyncram_component.intended_device_family = "Cyclone II",
        altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
        altsyncram_component.lpm_type = "altsyncram",
        altsyncram_component.numwords_a = 32,
        altsyncram_component.operation_mode = "SINGLE_PORT",
        altsyncram_component.outdata_aclr_a = "NONE",
        altsyncram_component.outdata_reg_a = "UNREGISTERED",
        altsyncram_component.power_up_uninitialized = "FALSE",
        altsyncram_component.ram_block_type = "M4K",
        altsyncram_component.widthad_a = 5,
        altsyncram_component.width_a = 8,
        altsyncram_component.width_byteena_a = 1;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL address[4..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf

Part II 验证part I的RAM

 

    本练习验证part I的RAM，即在DE2上用拨动开关写一部分数据到RAM，并读出，显示在数码管上。

代码part II：

//part 2 在DE2上验证Part的设计
//引脚说明：
//    input:    SW7-0 --DataIn        SW15-11--Address        SW17--Write        KEY0--Clock
//    output :    HEX7-6--Address        HEX5-4--DataIn        HEX1-0--DataOut        LEDG0--Write

module part2(
                        input [17:0] SW,
                        input [0:0] KEY,
                        output [0:0] LEDG,
                        output [0:6] HEX7,HEX6,HEX5,HEX4,HEX1,HEX0
                        );
                        
wire [7:0] DataOut;
                        
ramlpm u0(
                    .address(SW[15:11]),
                    .clock(KEY),
                    .data(SW[7:0]),
                    .wren(SW[17]),
                    .q(DataOut[7:0])
                    );
                    
assign LEDG=SW[17];        //Write的标记

//调用7-seg显示模块
seg_lut h5(HEX5,SW[7:4]);
seg_lut h4(HEX4,SW[3:0]);

seg_lut h7(HEX7,{{3{1'b0}},SW[15]});
seg_lut h6(HEX6,SW[14:11]);

seg_lut h1(HEX1,DataOut[7:4]);
seg_lut h0(HEX0,DataOut[3:0]);

endmodule

//7-seg

module seg_lut(oseg,idig);
input [3:0] idig;
output reg  [0:6] oseg;

always @(idig)
    case(idig)
        4'h1:    oseg=7'b100_1111;                //            --------0--------
        4'h2:    oseg=7'b001_0010;                //            |                        |
        4'h3:    oseg=7'b000_0110;                //            |                        |    1
        4'h4:    oseg=7'b100_1100;                //            |    5                    |
        4'h5:    oseg=7'b010_0100;                //            |                        |
        4'h6:    oseg=7'b010_0000;                //            --------6--------
        4'h7:    oseg=7'b000_1111;                //            |                        |
        4'h8:    oseg=7'b000_0000;                //            |                        |
        4'h9:    oseg=7'b000_1100;                //            |    4                    |    2
        4'hA:    oseg=7'b000_1000;                //            |                        |
        4'hb:    oseg=7'b110_0000;                //            --------3---------
        4'hC:    oseg=7'b011_0001;        
        4'hd:    oseg=7'b100_0010;
        4'hE:    oseg=7'b011_0000;
        4'hF:    oseg=7'b011_1000;
        default:    oseg=7'b111_1111;
    endcase

endmodule
    

Part III 自己编写RAM

 

    用多维数组定义存储器。32X8-bit的RAM可以定义为32X8的数组，如：

    reg [7:0] memory_array [31:0];

    对于Cyclone II系列的FPGA，实现这种数组可用触发器或M4K存储器块。确保使用M4K实现有两种方法：一是调用LPM库，二是用适当形式的Verilog代码定义RAM，这部分可查阅Quartus II 的帮助，搜索“Inferred memory”。

代码part 3：

module part3(
                        input [17:0] SW,
                        input [0:0] KEY,
                        output [0:0] LEDG,
                        output [0:6] HEX7,HEX6,HEX5,HEX4,HEX1,HEX0
                        );
                        
wire [7:0] DataOut;
                        
ram_single u0(
                    .a(SW[15:11]),
                    .clk(KEY),
                    .d(SW[7:0]),
                    .we(SW[17]),
                    .q(DataOut[7:0])
                    );
                    
assign LEDG=SW[17];        //Write的标记

//调用7-seg显示模块
seg_lut h5(HEX5,SW[7:4]);
seg_lut h4(HEX4,SW[3:0]);

seg_lut h7(HEX7,{{3{1'b0}},SW[15]});
seg_lut h6(HEX6,SW[14:11]);

seg_lut h1(HEX1,DataOut[7:4]);
seg_lut h0(HEX0,DataOut[3:0]);

endmodule

//7-seg

module seg_lut(oseg,idig);
input [3:0] idig;
output reg  [0:6] oseg;

always @(idig)
    case(idig)
        4'h1:    oseg=7'b100_1111;                //            --------0--------
        4'h2:    oseg=7'b001_0010;                //            |                        |
        4'h3:    oseg=7'b000_0110;                //            |                        |    1
        4'h4:    oseg=7'b100_1100;                //            |    5                    |
        4'h5:    oseg=7'b010_0100;                //            |                        |
        4'h6:    oseg=7'b010_0000;                //            --------6--------
        4'h7:    oseg=7'b000_1111;                //            |                        |
        4'h8:    oseg=7'b000_0000;                //            |                        |
        4'h9:    oseg=7'b000_1100;                //            |    4                    |    2
        4'hA:    oseg=7'b000_1000;                //            |                        |
        4'hb:    oseg=7'b110_0000;                //            --------3---------
        4'hC:    oseg=7'b011_0001;        
        4'hd:    oseg=7'b100_0010;
        4'hE:    oseg=7'b011_0000;
        4'hF:    oseg=7'b011_1000;
        default:    oseg=7'b111_1111;
    endcase

endmodule

//32*8 bit RAM

module ram_single(q,a,d,we,clk);
output reg [7:0] q;
input [7:0] d;
input [4:0] a;
input we,clk;

reg [7:0] mem [31:0] ;

always @(posedge clk)
begin
    if(we)
        mem[a]<=d;
    q<=mem[a];
end

endmodule

RAM Summary

与part 2的区别，读出RAM的数据慢一个时钟。

Part IV 使用SRAM

    本练习使用DE2上的SRAM—IS61LV25616AL-10.其参数可查看数据手册。为简化设计，控制端口除WE外，都缺省有效，即赋0值。

代码part 4：

//练习SRAM的读/写功能,通过FPGA控制SRAM
//引脚说明：
//---------------------------------------------------------
//    SW[17]                write
//    SW[15:11]            address
//    SW[7:0]                datain
//    KEY[1]                    rst_n
// KEY[0]                    clk

module part4(
                        input [17:0] SW,
                        input [1:0] KEY,                        //rst_n,clk
                        output [0:0] LEDG,
                        output [0:6] HEX7,HEX6,HEX5,HEX4,HEX1,HEX0,
                        
                        //SRAM pors
                        output [17:0] SRAM_ADDR,            //address
                        inout [15:0] SRAM_DQ,            //datain , dataout
                        output SRAM_CE_N,                    //chip enable
                                SRAM_OE_N,                    //output enable
                                SRAM_WE_N,                    //write enable
                                SRAM_UB_N,                    //upper byte
                                SRAM_LB_N                        //lower byte
                        );
                        
wire [7:0] DataOut,DataIn;
wire [4:0] address;
wire [15:0] DataIn_reg;
wire clk,rst_n,write,ce_n;
                    
assign clk=KEY[0];
assign rst_n=KEY[1];

assign write=SW[17];
regne #(.n(1) ) r0(write,clk,rst_n,1'b1,SRAM_WE_N);        //同步write

assign address=SW[15:11];
regne #(.n(5)) r1(address,clk,rst_n,1'b1,SRAM_ADDR[4:0]);        //同步address
assign SRAM_ADDR[17:5]=13'b0;

assign DataIn=SW[7:0];                                                            
regne #(.n(8)) r2(DataIn,clk,rst_n,1'b1,DataIn_reg[7:0]);            //同步DataIn
assign DataIn_reg[15:8]=8'b0;

assign SRAM_DQ=(SRAM_WE_N==0)?DataIn_reg:16'bz;

assign DataOut=SRAM_DQ[7:0];

regne #(.n(1)) r3(1'b1,clk,rst_n,1'b1,ce_n);            //CE初始化，上电为无效，避免写入
assign SRAM_CE_N=~ce_n;

assign 
          SRAM_OE_N=1'b0,            
          SRAM_UB_N=1'b0,
          SRAM_LB_N=1'b0;
          
assign LEDG=SW[17];        //Write的标记

//调用7-seg显示模块
seg_lut h5(HEX5,DataIn[7:4]);    //DataIn
seg_lut h4(HEX4,DataIn[3:0]);

seg_lut h7(HEX7,{{3{1'b0}},address[4]});        //address
seg_lut h6(HEX6,address[3:0]);

seg_lut h1(HEX1,DataOut[7:4]);            //DataOut
seg_lut h0(HEX0,DataOut[3:0]);

endmodule

//7-seg

module seg_lut(oseg,idig);
input [3:0] idig;
output reg  [0:6] oseg;

always @(idig)
    case(idig)
        4'h0:    oseg=7'b000_0001;
        4'h1:    oseg=7'b100_1111;                //            --------0--------
        4'h2:    oseg=7'b001_0010;                //            |                        |
        4'h3:    oseg=7'b000_0110;                //            |                        |    1
        4'h4:    oseg=7'b100_1100;                //            |    5                    |
        4'h5:    oseg=7'b010_0100;                //            |                        |
        4'h6:    oseg=7'b010_0000;                //            --------6--------
        4'h7:    oseg=7'b000_1111;                //            |                        |
        4'h8:    oseg=7'b000_0000;                //            |                        |
        4'h9:    oseg=7'b000_1100;                //            |    4                    |    2
        4'hA:    oseg=7'b000_1000;                //            |                        |
        4'hb:    oseg=7'b110_0000;                //            --------3---------
        4'hC:    oseg=7'b011_0001;        
        4'hd:    oseg=7'b100_0010;
        4'hE:    oseg=7'b011_0000;
        4'hF:    oseg=7'b011_1000;
        default:    oseg=7'b111_1111;
    endcase

endmodule

//register 用来同步输入信号

module regne(r,clk,rst_n,e,q);
parameter n=7;
input [n-1:0] r;
input clk,rst_n,e;
output reg [n-1:0] q;

always @(posedge clk)
begin
    if(rst_n==0)
        q<={n{1'b0}};
    else if(e)
        q<=r;
end

endmodule
        

Part V 用LPM创建双口RAM

    所谓双口，即读/写的地址端口分开，即选择Simple dual-port mode。本练习可对存储器初始化，建立一个mif文件。最终在数码管上实现循环显示RAM的数据和地址，间隔为1s。

代码part 5：

//part 5 
// 创建一个读写分开控制的RAM，要求上电后，读地址和其对应的数据以1s的间隔
//循环显示在HEX3-2和HEX1-0上，通过写地址和写控制，可以随时修改对应地址
//的内容。RAM用mif文件初始化。

//引脚说明：
//-------------------------------------------------------------------
//        SW[17]        write_en
//        SW[15:11]    address
//        SW[7:0]        datain
//        LEDG0        write
//        HEX7-6        address
//        HEX5-4        datain
//        HEX3-2        read_address
//        HEX1-0        dataout
//        KEY0            rst_n
//        CLOCK_50    clk

module part5(    
                    input CLOCK_50,
                    input [0:0] KEY,
                    input [17:0] SW,
                    output [0:6] HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0,
                    output [0:0] LEDG
                    );
                    
                    wire clk,rst_n,write,write_sync;
                    wire [4:0] write_address,write_address_sync;
                    wire [7:0] datain,datain_sync,dataout;
                    
                    assign rst_n=KEY[0];
                    assign clk=CLOCK_50;
                    
                    //同步输入信号
                    
                    regne #(.n(1)) r0(SW[17],clk,rst_n,1'b1,write_sync);
                    regne #(.n(1)) r1(write_sync,clk,rst_n,1'b1,write);
                    
                    regne #(.n(5)) r2(SW[15:11],clk,rst_n,1'b1,write_address_sync);
                    regne #(.n(5)) r3(write_address_sync,clk,rst_n,1'b1,write_address);
                    
                    regne #(.n(8)) r4(SW[7:0],clk,rst_n,1'b1,datain_sync);
                    regne #(.n(8)) r5(datain_sync,clk,rst_n,1'b1,datain);
                    
                    //分频，产生约1s的时钟
                    
                    parameter m=26;        //（2^26-1）*20*10^(-9)=1.3s
                    reg [m-1:0] div_count;
                    reg [4:0] read_address;    //0-31
                    
                    //寻址计数
                    
                    always @(posedge clk)
                        div_count<=div_count+1'b1;
                    always @(posedge clk)
                        if(!rst_n)
                            read_address<=5'b0;
                        else if(div_count==0)        //每过约1s
                            read_address<=read_address+1'b1;
                            
                    //引用LPM
                    ramlpm u0(
                                    .clock(clk),
                                    .data(datain),
                                    .rdaddress(read_address),
                                    .wraddress(write_address),
                                    .wren(write),
                                    .q(dataout)
                                    );
                                    
                                    
                    assign LEDG=write;        //Write的标记

                    //调用7-seg显示模块
                    seg_lut h5(HEX5,datain[7:4]);    //DataIn
                    seg_lut h4(HEX4,datain[3:0]);

                    seg_lut h7(HEX7,{{3{1'b0}},write_address[4]});        //address
                    seg_lut h6(HEX6,write_address[3:0]);

                    seg_lut h1(HEX1,dataout[7:4]);            //DataOut
                    seg_lut h0(HEX0,dataout[3:0]);

                    seg_lut h3(HEX3,{{3{1'b0}},read_address[4]});        //address
                    seg_lut h2(HEX2,read_address[3:0]);
                    
endmodule

//7-seg

module seg_lut(oseg,idig);
input [3:0] idig;
output reg  [0:6] oseg;

always @(idig)
    case(idig)
        4'h0:    oseg=7'b000_0001;
        4'h1:    oseg=7'b100_1111;                //            --------0--------
        4'h2:    oseg=7'b001_0010;                //            |                        |
        4'h3:    oseg=7'b000_0110;                //            |                        |    1
        4'h4:    oseg=7'b100_1100;                //            |    5                    |
        4'h5:    oseg=7'b010_0100;                //            |                        |
        4'h6:    oseg=7'b010_0000;                //            --------6--------
        4'h7:    oseg=7'b000_1111;                //            |                        |
        4'h8:    oseg=7'b000_0000;                //            |                        |
        4'h9:    oseg=7'b000_1100;                //            |    4                    |    2
        4'hA:    oseg=7'b000_1000;                //            |                        |
        4'hb:    oseg=7'b110_0000;                //            --------3---------
        4'hC:    oseg=7'b011_0001;        
        4'hd:    oseg=7'b100_0010;
        4'hE:    oseg=7'b011_0000;
        4'hF:    oseg=7'b011_1000;
        default:    oseg=7'b111_1111;
    endcase

endmodule

//register 用来同步输入信号

module regne(r,clk,rst_n,e,q);
parameter n=7;
input [n-1:0] r;
input clk,rst_n,e;
output reg [n-1:0] q;

always @(posedge clk)
begin
    if(rst_n==0)
        q<={n{1'b0}};
    else if(e)
        q<=r;
end

endmodule                
                    
                    
                    

// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram 

// ============================================================
// File Name: ramlpm.v
// Megafunction Name(s):
//             altsyncram
//
// Simulation Library Files(s):
//             altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ramlpm (
    clock,
    data,
    rdaddress,
    wraddress,
    wren,
    q);

    input      clock;
    input    [7:0]  data;
    input    [4:0]  rdaddress;
    input    [4:0]  wraddress;
    input      wren;
    output    [7:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
    tri1      wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

    wire [7:0] sub_wire0;
    wire [7:0] q = sub_wire0[7:0];

    altsyncram    altsyncram_component (
                .wren_a (wren),
                .clock0 (clock),
                .address_a (wraddress),
                .address_b (rdaddress),
                .data_a (data),
                .q_b (sub_wire0),
                .aclr0 (1'b0),
                .aclr1 (1'b0),
                .addressstall_a (1'b0),
                .addressstall_b (1'b0),
                .byteena_a (1'b1),
                .byteena_b (1'b1),
                .clock1 (1'b1),
                .clocken0 (1'b1),
                .clocken1 (1'b1),
                .clocken2 (1'b1),
                .clocken3 (1'b1),
                .data_b ({8{1'b1}}),
                .eccstatus (),
                .q_a (),
                .rden_a (1'b1),
                .rden_b (1'b1),
                .wren_b (1'b0));
    defparam
        altsyncram_component.address_reg_b = "CLOCK0",
        altsyncram_component.clock_enable_input_a = "BYPASS",
        altsyncram_component.clock_enable_input_b = "BYPASS",
        altsyncram_component.clock_enable_output_a = "BYPASS",
        altsyncram_component.clock_enable_output_b = "BYPASS",
        altsyncram_component.init_file = "ramlpm.mif",
        altsyncram_component.intended_device_family = "Cyclone II",
        altsyncram_component.lpm_type = "altsyncram",
        altsyncram_component.numwords_a = 32,
        altsyncram_component.numwords_b = 32,
        altsyncram_component.operation_mode = "DUAL_PORT",
        altsyncram_component.outdata_aclr_b = "NONE",
        altsyncram_component.outdata_reg_b = "UNREGISTERED",
        altsyncram_component.power_up_uninitialized = "FALSE",
        altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
        altsyncram_component.widthad_a = 5,
        altsyncram_component.widthad_b = 5,
        altsyncram_component.width_a = 8,
        altsyncram_component.width_b = 8,
        altsyncram_component.width_byteena_a = 1;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "ramlpm.mif"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "ramlpm.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL rdaddress[4..0]
// Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL wraddress[4..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0
// Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf

Part VI 单口复用RAM

    修改Part V的RAM，用多路器实现一个地址端口复用。在LPM里选择Allow In-system Memory Content Editor to capture and update content independently of the system clock。存储器ID设为32X8.

    调用这个RAM模块，实现与Part 5同样的功能。

    在使用In-System Memory Content Editor之前，需要设置参数。Assignment / setting / Analysis & Synthesis Setting / Defualt Parameters 添加一个参数CYCLONEII_SAFE_WRITE, 值为RESTRUCTURE。

    编译、测试。与Part 5的结果比较。

    Tools / In-System Memory Content Editor读取和修改RAM的内容，并与数码管的显示比较。

代码part 6；

//part 6 单端口的RAM，读写共用地址总线。练习In-system memory content editor
///引脚说明：
//-------------------------------------------------------------------
//        SW[17]        write_en
//        SW[15:11]    address
//        SW[7:0]        datain
//        LEDG0        write
//        HEX7-6        address
//        HEX5-4        datain
//        HEX3-2        read_address
//        HEX1-0        dataout
//        KEY0            rst_n
//        CLOCK_50    clk

module part6(
                        input CLOCK_50,
                    input [0:0] KEY,
                    input [17:0] SW,
                    output [0:6] HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0,
                    output [0:0] LEDG
                    );
                    
                    wire clk,rst_n,write,write_sync;
                    wire [4:0] write_address,write_address_sync;
                    wire [7:0] datain,datain_sync,dataout;
                    
                    assign rst_n=KEY[0];
                    assign clk=CLOCK_50;
                    
                    //同步输入信号
                    
                    regne #(.n(1)) r0(SW[17],clk,rst_n,1'b1,write_sync);
                    regne #(.n(1)) r1(write_sync,clk,rst_n,1'b1,write);
                    
                    regne #(.n(5)) r2(SW[15:11],clk,rst_n,1'b1,write_address_sync);
                    regne #(.n(5)) r3(write_address_sync,clk,rst_n,1'b1,write_address);
                    
                    regne #(.n(8)) r4(SW[7:0],clk,rst_n,1'b1,datain_sync);
                    regne #(.n(8)) r5(datain_sync,clk,rst_n,1'b1,datain);
                    
                    //分频，产生约1s的时钟
                    
                    parameter m=26;        //（2^26-1）*20*10^(-9)=1.3s
                    reg [m-1:0] div_count;
                    reg [4:0] read_address;    //0-31
                    
                    //寻址计数
                    
                    always @(posedge clk)
                        div_count<=div_count+1'b1;
                    always @(posedge clk)
                        if(!rst_n)
                            read_address<=5'b0;
                        else if(div_count==0)        //每过约1s
                            read_address<=read_address+1'b1;
                            
                    //用multiplexer决定地址
                    wire [4:0] address;
                    assign address=(write==1'b1)?write_address:read_address;    
                            
                    //引用LPM
                    ramlpm u0(
                                    .clock(clk),
                                    .data(datain),
                                    .address(address),
                                    .wren(write),
                                    .q(dataout)
                                    );
                                    
                                    
                    assign LEDG=write;        //Write的标记

                    //调用7-seg显示模块
                    seg_lut h5(HEX5,datain[7:4]);    //DataIn
                    seg_lut h4(HEX4,datain[3:0]);

                    seg_lut h7(HEX7,{{3{1'b0}},write_address[4]});        //address
                    seg_lut h6(HEX6,write_address[3:0]);

                    seg_lut h1(HEX1,dataout[7:4]);            //DataOut
                    seg_lut h0(HEX0,dataout[3:0]);

                    seg_lut h3(HEX3,{{3{1'b0}},read_address[4]});        //address
                    seg_lut h2(HEX2,read_address[3:0]);
                    
endmodule

//7-seg

module seg_lut(oseg,idig);
input [3:0] idig;
output reg  [0:6] oseg;

always @(idig)
    case(idig)
        4'h0:    oseg=7'b000_0001;
        4'h1:    oseg=7'b100_1111;                //            --------0--------
        4'h2:    oseg=7'b001_0010;                //            |                        |
        4'h3:    oseg=7'b000_0110;                //            |                        |    1
        4'h4:    oseg=7'b100_1100;                //            |    5                    |
        4'h5:    oseg=7'b010_0100;                //            |                        |
        4'h6:    oseg=7'b010_0000;                //            --------6--------
        4'h7:    oseg=7'b000_1111;                //            |                        |
        4'h8:    oseg=7'b000_0000;                //            |                        |
        4'h9:    oseg=7'b000_1100;                //            |    4                    |    2
        4'hA:    oseg=7'b000_1000;                //            |                        |
        4'hb:    oseg=7'b110_0000;                //            --------3---------
        4'hC:    oseg=7'b011_0001;        
        4'hd:    oseg=7'b100_0010;
        4'hE:    oseg=7'b011_0000;
        4'hF:    oseg=7'b011_1000;
        default:    oseg=7'b111_1111;
    endcase

endmodule

//register 用来同步输入信号

module regne(r,clk,rst_n,e,q);
parameter n=7;
input [n-1:0] r;
input clk,rst_n,e;
output reg [n-1:0] q;

always @(posedge clk)
begin
    if(rst_n==0)
        q<={n{1'b0}};
    else if(e)
        q<=r;
end

endmodule                

ramlpm.v

// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram 

// ============================================================
// File Name: ramlpm.v
// Megafunction Name(s):
//             altsyncram
//
// Simulation Library Files(s):
//             altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 222 10/21/2009 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ramlpm (
    address,
    clock,
    data,
    wren,
    q);

    input    [4:0]  address;
    input      clock;
    input    [7:0]  data;
    input      wren;
    output    [7:0]  q;

    wire [7:0] sub_wire0;
    wire [7:0] q = sub_wire0[7:0];

    altsyncram    altsyncram_component (
                .wren_a (wren),
                .clock0 (clock),
                .address_a (address),
                .data_a (data),
                .q_a (sub_wire0),
                .aclr0 (1'b0),
                .aclr1 (1'b0),
                .address_b (1'b1),
                .addressstall_a (1'b0),
                .addressstall_b (1'b0),
                .byteena_a (1'b1),
                .byteena_b (1'b1),
                .clock1 (1'b1),
                .clocken0 (1'b1),
                .clocken1 (1'b1),
                .clocken2 (1'b1),
                .clocken3 (1'b1),
                .data_b (1'b1),
                .eccstatus (),
                .q_b (),
                .rden_a (1'b1),
                .rden_b (1'b1),
                .wren_b (1'b0));
    defparam
        altsyncram_component.clock_enable_input_a = "BYPASS",
        altsyncram_component.clock_enable_output_a = "BYPASS",
        altsyncram_component.init_file = "../part5/ramlpm.mif",
        altsyncram_component.intended_device_family = "Cyclone II",
        altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=32x8",
        altsyncram_component.lpm_type = "altsyncram",
        altsyncram_component.numwords_a = 32,
        altsyncram_component.operation_mode = "SINGLE_PORT",
        altsyncram_component.outdata_aclr_a = "NONE",
        altsyncram_component.outdata_reg_a = "UNREGISTERED",
        altsyncram_component.power_up_uninitialized = "FALSE",
        altsyncram_component.ram_block_type = "M4K",
        altsyncram_component.widthad_a = 5,
        altsyncram_component.width_a = 8,
        altsyncram_component.width_byteena_a = 1;


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
// Retrieval info: PRIVATE: JTAG_ID STRING "32x8"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../part5/ramlpm.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "5"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../part5/ramlpm.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=32x8"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 5 0 INPUT NODEFVAL address[4..0]
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL wren
// Retrieval info: CONNECT: @address_a 0 0 5 0 address 0 0 5 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ramlpm_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf

Part VII 用DE2控制面板查看并修改SRAM的内容

    本练习借助DE2 控制面板这个工具来对片外存储器初始化和查看、修改。

    DE2 control panel的使用方法可查阅用户手册。下载相应的电路，打开应用程序，启动接口，即可实现对SRAM的控制。

代码part 7:

//练习SRAM的读/写功能,通过FPGA控制SRAM和通过DE2 control pannel控制SRAM

///引脚说明：
//-------------------------------------------------------------------
//        SW[17]        write_en
//        SW[15:11]    address
//        SW[7:0]        datain
//        LEDG0        write
//        HEX7-6        address
//        HEX5-4        datain
//        HEX3-2        read_address
//        HEX1-0        dataout
//        KEY0            rst_n
//        CLOCK_50    clk

module part7(
                        input CLOCK_50,
                        input [17:0] SW,
                        input [0:0] KEY,                        //rst_n
                        output [0:0] LEDG,
                        output [0:6] HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0,
                        
                        //SRAM pors
                        output [17:0] SRAM_ADDR,            //address
                        inout [15:0] SRAM_DQ,            //datain , dataout
                        output SRAM_CE_N,                    //chip enable
                                SRAM_OE_N,                    //output enable
                                SRAM_WE_N,                    //write enable
                                SRAM_UB_N,                    //upper byte
                                SRAM_LB_N                        //lower byte
                        );
                        

                        wire rst_n,clk,writen_sync,ce,ce1,ce2;
                        wire [7:0] datain,datain_sync,dataout;
                        wire [4:0] write_address,write_address_sync;
                    
assign clk=CLOCK_50;
assign rst_n=KEY[0];

//同步输入信号

regne #(.n(1)) r0(!SW[17],clk,rst_n,1'b1,writen_sync);
regne #(.n(1) ) r1(writen_sync,clk,rst_n,1'b1,SRAM_WE_N);        //同步write

regne #(.n(5)) r2(SW[15:11],clk,rst_n,1'b1,write_address_sync);
regne #(.n(5)) r3(write_address_sync,clk,rst_n,1'b1,write_address);        //同步address

regne #(.n(8)) r4(SW[7:0],clk,rst_n,1'b1,datain_sync);                                                            
regne #(.n(8)) r5(datain_sync,clk,rst_n,1'b1,datain);            //同步DataIn

//分频，产生约1s的时钟
parameter m=26;
reg [m-1:0] div_count;
reg [4:0] read_address;

//寻址
always @(posedge clk)
    div_count<=div_count+1;
    
always @(posedge clk)
    if(!rst_n)
        read_address<=5'b0;
    else if(div_count==0)
        read_address<=read_address+1'b1;

//读/写选择        
assign SRAM_ADDR=(SRAM_WE_N==1'b0)?{13'b0,write_address}:{13'b0,read_address};
        
assign SRAM_DQ=(SRAM_WE_N==1'b0)?{8'b0,datain}:16'bz;

assign dataout=SRAM_DQ[7:0];

regne #(.n(1)) r6(1'b1,clk,rst_n,1'b1,ce1);            //CE初始化，上电后2个时钟，避免写入
regne #(.n(1)) r7(ce1,clk,rst_n,1'b1,ce2);
regne #(.n(1)) r8(ce2,clk,rst_n,1'b1,ce);
assign SRAM_CE_N=~ce;

assign 
          SRAM_OE_N=1'b0,            
          SRAM_UB_N=1'b0,
          SRAM_LB_N=1'b0;
          
assign LEDG=SRAM_WE_N;        //Write的标记

//调用7-seg显示模块
seg_lut h5(HEX5,datain[7:4]);    //DataIn
seg_lut h4(HEX4,datain[3:0]);

seg_lut h7(HEX7,{{3{1'b0}},write_address[4]});        //address
seg_lut h6(HEX6,write_address[3:0]);

seg_lut h1(HEX1,dataout[7:4]);            //DataOut
seg_lut h0(HEX0,dataout[3:0]);

seg_lut h3(HEX3,{3'b0,read_address[4]});            //read_address
seg_lut h2(HEX2,read_address[3:0]);

endmodule

//7-seg

module seg_lut(oseg,idig);
input [3:0] idig;
output reg  [0:6] oseg;

always @(idig)
    case(idig)
        4'h0:    oseg=7'b000_0001;
        4'h1:    oseg=7'b100_1111;                //            --------0--------
        4'h2:    oseg=7'b001_0010;                //            |                        |
        4'h3:    oseg=7'b000_0110;                //            |                        |    1
        4'h4:    oseg=7'b100_1100;                //            |    5                    |
        4'h5:    oseg=7'b010_0100;                //            |                        |
        4'h6:    oseg=7'b010_0000;                //            --------6--------
        4'h7:    oseg=7'b000_1111;                //            |                        |
        4'h8:    oseg=7'b000_0000;                //            |                        |
        4'h9:    oseg=7'b000_1100;                //            |    4                    |    2
        4'hA:    oseg=7'b000_1000;                //            |                        |
        4'hb:    oseg=7'b110_0000;                //            --------3---------
        4'hC:    oseg=7'b011_0001;        
        4'hd:    oseg=7'b100_0010;
        4'hE:    oseg=7'b011_0000;
        4'hF:    oseg=7'b011_1000;
        default:    oseg=7'b111_1111;
    endcase

endmodule

//register 用来同步输入信号

module regne(r,clk,rst_n,e,q);
parameter n=7;
input [n-1:0] r;
input clk,rst_n,e;
output reg [n-1:0] q;

always @(posedge clk)
begin
    if(rst_n==0)
        q<={n{1'b0}};
    else if(e)
        q<=r;
end

endmodule
        

Conclue

    以上7个小练习逐步熟悉对RAM的操作。有意思的是part 7的控制面板。有UI，有驱动电路。