一、概述
The Universal Asynchronous Receiver and Transmitter (UART) in S5PV210 provide four independent asynchronous, and serial input/output (I/O) ports. All the ports operate in an interrupt-based or a DMA-based mode. The UART generates an interrupt or a DMA request to transfer data to and from the CPU and the UART. The UART supports bit rates up to 3Mbps. Each UART channel contains two FIFOs to receive and transmit data: 256 bytes in ch0, 64 bytes in ch1 and 16 bytes in ch2 and ch3.
UART includes programmable baud rates, infrared (IR) transmitter/receiver, one or two stop bit insertion, 5-bit, 6-bit, 7-bit, or 8-bit data width and parity checking.
Each UART contains a baud-rate generator, a transmitter, a receiver and a control unit, as shown in Figure 1-1. The baud-rate generator uses PCLK or SCLK_UART. The transmitter and the receiver contain FIFOs and data shifters. The data to be transmitted is written to Tx FIFO, and copied to the transmit shifter. The data is then shifted out by the transmit data pin (TxDn). The received data is shifted from the receive data pin (RxDn), and copied to Rx FIFO from the shifter.
二、寄存器
