任意时钟分频

// clock divider
`timescale 1ns/1ps
module clgen
#(parameter DIVIDER_LEN = 8)
(
  input wire clk_in,
  input wire rst,
  input wire enable,
  input wire [DIVIDER_LEN-1:0] divider,
  output wire clk_out
);

wire odd_or_even;
wire [DIVIDER_LEN-1:0] cnt_zero;
wire [DIVIDER_LEN-1:0] cnt_one;
reg [DIVIDER_LEN-1:0] cnt_pos;
reg [DIVIDER_LEN-1:0] cnt_neg;
reg flag_pos;
reg flag_neg;

assign odd_or_even = divider[0];
assign cnt_zero = odd_or_even ? (divider-1)>>1:divider[DIVIDER_LEN-1:1]-1 ;
assign cnt_one = (divider-1);

always @(posedge clk_in or posedge rst)
if(rst)
      cnt_pos <= {DIVIDER_LEN{1'b0}};
else begin
    if(cnt_pos >= cnt_one)
        cnt_pos <= {DIVIDER_LEN{1'b0}};
    else if(enable)
        cnt_pos <= cnt_pos + 1;
end

always @(negedge clk_in or posedge rst)
if(rst)
      cnt_neg <= {DIVIDER_LEN{1'b0}};
else begin
    if(cnt_neg >= cnt_one)
        cnt_neg <= {DIVIDER_LEN{1'b0}};
    else if(enable)
        cnt_neg <= cnt_neg + 1;

end

always @(posedge clk_in or posedge rst)
if(rst)
      flag_pos <= 1'b0;
else begin
    if(cnt_pos == cnt_zero)
      flag_pos <= 1'b0;
    else
      if(cnt_pos == cnt_one)
      flag_pos <= 1'b1;
end

always @(negedge clk_in or posedge rst)
if(rst)
      flag_neg <= 1'b0;
else begin
    if(cnt_neg == cnt_zero)
      flag_neg <= 1'b0;
    else
      if(cnt_neg == cnt_one)
      flag_neg <= 1'b1;
end

assign clk_out = odd_or_even ?( flag_pos & flag_neg) : flag_pos;


endmodule