异步采样模块
在实际中，外部输入的异步信号需要经过系统时钟的同步化，且将输入的异步信号整形成一个时钟的脉冲信号，如下图所示 
在此使用Verilog将外部异步信号进行同步整形：
module clk_syn(
clk,
reset,
s_in,
s_out
);
// --------------Port Declaration----------------------
input clk;
input reset;
input s_in;
output s_out;
//--------------Port data type declaration-------------
//--------------Define Parameter-----------------------
//--------------Internal Registers---------------------
reg s_t1;
reg s_t2;
//--------------Code Starts Here-----------------------
always @ (posedge clk) begin
if(!reset) begin
s_t1 <= 0;
s_t2 <= 0;
end
else begin
s_t1 <= s_in;
s_t2 <= s_t1;
end
end
assign s_out = s_t1 & (!s_t2);
endmodule
激励程序为：
///////////////////////////////////////////////////////////////////////
/////////
module clk_syn_tb;
// Inputs
reg clk;
reg reset;
reg s_in;
// Outputs
wire s_out;
// Instantiate the Unit Under Test (UUT)
clk_syn uut (
.clk(clk),
.reset(reset),
.s_in(s_in),
.s_out(s_out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
s_in = 0;
// Wait 100 ns for global reset to finish
#100;
reset = 1;
#50;
s_in = 1;
#100;
s_in = 0;
#50;
s_in = 1;
#100
s_in = 0;
// Add stimulus here
end
always #6 clk = ~clk;
endmodule
时序图为：
综合后的ＲＴＬ为：
仿真波形：
注意：综合工具采用Xilinx ISE Design Suite 12.4自带的综合工具ＸＳＴ，仿真采用Xilinx ISE Design Suite 12.4自带的仿真工具Ｉｓｉｍ。