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  • 利用状态机(FSM)进行简单的uart串口发送数据

    module uart_tx(clk,rst_n,key,txd);
    
    input clk;
    input rst_n;
    input key;
    output reg txd;
    
    reg[3:0] state;
    reg[15:0] bit_timer;
    wire[7:0] tx_data;
    assign tx_data=8'h5a; 
    
    
    parameter s_idle=4'd0;
    parameter s_start=4'd1;
    parameter s_bit0=4'd2;
    parameter s_bit1=4'd3;
    parameter s_bit2=4'd4;
    parameter s_bit3=4'd5;
    parameter s_bit4=4'd6;
    parameter s_bit5=4'd7;
    parameter s_bit6=4'd8;
    parameter s_bit7=4'd9;
    parameter s_stop=4'd10;
    
    always@(posedge clk or negedge rst_n)
    begin
        if(!rst_n)
        begin
             state<=s_idle;
             bit_timer<=16'd0;
             txd<=1'b1; 
        end
        else
        begin
            case(state)
            
            s_idle:
            begin
                txd<=1'b1;
                if(!key)
                state<=s_start;
                else
                state<=state;
            end
            
            
            s_start:
            begin
                txd<=1'b0;
                if(bit_timer==16'd5208)
                begin
                state<=s_bit0;
                bit_timer<=16'd0;
                end
                else
                begin
                state<=state;
                bit_timer=bit_timer+16'd1;
                end
            end
            
            s_bit0:
            begin
                txd<=tx_data[0];
                if(bit_timer==16'd5208)
                begin
                state<=s_bit1;
                bit_timer<=16'd0;
                end
                else
                begin
                state<=state;
                bit_timer=bit_timer+16'd1;
                end
            end
            
             s_bit1:
            begin
                txd<=tx_data[1];
                if(bit_timer==16'd5208)
                begin
                state<=s_bit2;
                bit_timer<=16'd0;
                end
                else
                begin
                state<=state;
                bit_timer=bit_timer+16'd1;
                end
            end
            
            
            s_bit2:
            begin
                txd<=tx_data[2];
                if(bit_timer==16'd5208)
                begin
                state<=s_bit3;
                bit_timer<=16'd0;
                end
                else
                begin
                state<=state;
                bit_timer=bit_timer+16'd1;
                end
            end
            
            
             s_bit3:
            begin
                txd<=tx_data[3];
                if(bit_timer==16'd5208)
                begin
                state<=s_bit4;
                bit_timer<=16'd0;
                end
                else
                begin
                state<=state;
                bit_timer=bit_timer+16'd1;
                end
            end
            
            
             s_bit4:
            begin
                txd<=tx_data[4];
                if(bit_timer==16'd5208)
                begin
                state<=s_bit5;
                bit_timer<=16'd0;
                end
                else
                begin
                state<=state;
                bit_timer=bit_timer+16'd1;
                end
            end
            
            
             s_bit5:
            begin
                txd<=tx_data[5];
                if(bit_timer==16'd5208)
                begin
                state<=s_bit6;
                bit_timer<=16'd0;
                end
                else
                begin
                state<=state;
                bit_timer=bit_timer+16'd1;
                end
            end
            
            
             s_bit6:
            begin
                txd<=tx_data[6];
                if(bit_timer==16'd5208)
                begin
                state<=s_bit7;
                bit_timer<=16'd0;
                end
                else
                begin
                state<=state;
                bit_timer=bit_timer+16'd1;
                end
            end
            
            
             s_bit7:
            begin
                txd<=tx_data[7];
                if(bit_timer==16'd5208)
                begin
                state<=s_stop;
                bit_timer<=16'd0;
                end
                else
                begin
                state<=state;
                bit_timer=bit_timer+16'd1;
                end
            end
            
             s_stop:
            begin
                txd<=1'b1;
                if(bit_timer==16'd5208)
                begin
                state<=s_idle;
                bit_timer<=16'd0;
                end
                else
                begin
                state<=state;
                bit_timer=bit_timer+16'd1;
                end
            end
            
            default:
            begin
            state<=s_idle;
            end
            
            
            endcase
        end
            
        
    end
      
    endmodule
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  • 原文地址:https://www.cnblogs.com/jeavenwong/p/6772320.html
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