自己写的串口代码，高采样时钟

这几年一直在努力提高自己，从研究所出来后，由于工作的方向变了，自然就接触不了超大规模fpga了。也做不了fft和数字滤波器以及多相滤波等算法。转而在逻辑设计上更加深入的研究了。从千兆以太网的设计和mac的编写，以及sdram的另一种读写方式的研究，就是所谓的切换bank提高读写效率。

　　最近重新学习了51单片机，发现其实软件和硬件是想通的。软件的编码最后变成了rom里面的数字，硬件再从rom中读出数据到ram里去一条条执行。

　　今天我想分享下我写的串口控制程序，相比较于网上大多数的写法，我的独辟新境，有另一种风格。

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:45:55 11/03/2012 
// Design Name: 
// Module Name:    uart_rx 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module my_uart_rx(clk_50MHZ,rxd,baud_sample_num,rx_dout_r,valid_r);
        input clk_50MHZ;  // recieve data colock
        //input reset; // recieve data reset
        input rxd;   // wire for recieve data
        input [15:0] baud_sample_num;
        //output rx_ready_n; // recieve data ready signal
        output reg[7:0]rx_dout_r;  // recieve data out put
        output reg valid_r;
        reg[7:0]rx_dout;  // recieve data out put
        reg valid;

reg [15:0]counter=16'd0,num=16'd0;
reg rxd_r1,rxd_r2;
reg [3:0] i;

reg [1:0] mystate=2'b00;
parameter idle=2'b00;
parameter rx_data=2'b01;
parameter stop=2'b11;

reg counter_en;

always @(posedge clk_50MHZ)
if(valid) rx_dout_r<=rx_dout;
else rx_dout_r<=rx_dout_r;

always @(posedge clk_50MHZ)
 valid_r<=valid;

always @(posedge clk_50MHZ)
begin
    rxd_r1<=rxd;
    rxd_r2<=rxd_r1;
end

reg reset;
reg [3:0] cnt;
always @(posedge clk_50MHZ)
begin
     if(cnt<4'd15)begin reset<=1'b1;cnt<=cnt+1'b1;end
      else reset<=1'b0;
end

always @(posedge clk_50MHZ)
begin
    if(reset)mystate<=idle;
    else
        begin
         case(mystate)
            idle:
                begin
                    if(counter==baud_sample_num-1&&num>baud_sample_num/2)
                            mystate<=rx_data;
                    else     mystate<=idle;
                end
            rx_data:
                begin
                    if(counter==baud_sample_num-1&&i==7)
                            mystate<=stop;
                    else     mystate<=rx_data;
                end
         stop:            mystate<=idle;
          default:        mystate<=idle;
        endcase
    end
end


always @(posedge clk_50MHZ)
begin
    case(mystate)
    idle:
        begin
            if(!rxd_r1&&rxd_r2)
                        begin
                            counter_en<=1'b1;
                            counter<=16'd0;
                            
                        end
            else if(counter_en)
                       begin
                            if(counter<baud_sample_num-1)
                                    counter<=counter+1'b1;
                            else  
                                begin
                                     counter_en<=1'b0; 
                                     counter<=16'd0;
                                    
                                end
                        end
            end
     rx_data:
        begin
            if(counter<baud_sample_num-1)
                    counter<=counter+1'b1;
            else  
                begin
                    counter<=16'd0;
                end
          end
        stop:begin counter<=16'd0;counter_en<=1'b0;end
        default:begin counter<=16'd0;counter_en<=1'b0;end
    endcase
end

always @(posedge clk_50MHZ)
begin
    case(mystate)
    idle:
        begin
           i<=0;
            if(!rxd_r1&&rxd_r2)
                        begin
                            num<=16'd0;
                        end
            else if(counter_en)
                       begin
                           if(counter==baud_sample_num-1)num<=16'd0;
                            else if(!rxd_r2)num<=num+1'b1;
                            else num<=num;
                        end
                            
        end
     rx_data:
        begin
              if(counter==baud_sample_num-1)
                  begin
                        if(num>baud_sample_num/2)begin rx_dout[i]<=1'b1;i<=i+1'b1;num<=0;end
                        else begin rx_dout[i]<=1'b0;i<=i+1'b1;num<=0;end
                        
                        //rx_dout[i]<=rxd_r2;i<=i+1'b1;num<=0;
                    end
                else if(rxd_r2)num<=num+1'b1;
                else num<=num;
            end
        stop:begin num<=0;i<=0;end
    default:num<=0;
endcase
end

always @(posedge clk_50MHZ)
if(mystate==stop)valid<=1'b1;
else valid<=1'b0;

endmodule

module my_uart_tx(

input [11:0] last_rev_addr,

input clk,

input EPCS_EN,

input [15:0] baud_sample_num,

input [31:0]length,
        
input correct,
input correct_valid,

input rev_valid,

input [7:0] rev_data,
input [7:0] check_sum,

output reg txd,

output reg [10:0] raddr,
output reg rden,

output reg check_valid,
output reg send_reg_valid,
output reg [7:0] send_reg,

input tRL_valid,

input [15:0]temperature1,

input [15:0]temperature2,

input [15:0]TO,

input [15:0]RHO,

input [7:0]TSL
                        
    );


reg valid_a;



parameter idle=2'b00;
parameter send=2'b01;
parameter send_t=2'b10;


reg [1:0]mystate;
reg [3:0] cnt;
reg [15:0] counter;
reg reset;

reg [11:0]counter_a;
reg[7:0] send_rega[15:0];

reg [7:0] send_regc[32:0];

//2048+4
wire [31:0] tx_length=last_rev_addr+5/*synthesis syn_keep=1*/;

always @(posedge clk)
if(correct_valid)
 begin
    if(correct)begin
                    send_rega[0]<=8'h7E;
                         send_rega[1]<=8'h7E;
                         send_rega[2]<=8'h55;
                         send_rega[3]<=8'h3C;
                         send_rega[4]<=8'h00;
                         send_rega[5]<=8'h00;
                         send_rega[6]<=8'h00;
                         send_rega[7]<=8'h00;
                         
                         send_rega[8]<=tx_length[7:0];//8'h04;
                         send_rega[9]<=tx_length[15:8];//8'h08;
                         send_rega[10]<=tx_length[23:16];//8'h00;
                         send_rega[11]<=tx_length[31:24];//8'h00;
                         
                        send_rega[12]<= 8'h01;
                        send_rega[13]<=8'h00;
                        send_rega[14]<=8'h00;
                        send_rega[15]<=8'h00;
                    end
    else       begin
                    send_rega[0]<=8'h7E;
                         send_rega[1]<=8'h7E;
                         send_rega[2]<=8'h55;
                         send_rega[3]<=8'h3C;
                         send_rega[4]<=8'h00;
                         send_rega[5]<=8'h00;
                         send_rega[6]<=8'h00;
                         send_rega[7]<=8'h00;
                         
                         send_rega[8]<=tx_length[7:0];//8'h04;
                         send_rega[9]<=tx_length[15:8];//8'h08;
                         send_rega[10]<=tx_length[23:16];//8'h00;
                         send_rega[11]<=tx_length[31:24];//8'h00;
                         
                         send_rega[12]<= 8'h00;
                         send_rega[13]<=8'h00;
                         send_rega[14]<=8'h00;
                         send_rega[15]<=8'h00;
                    end
end


always @(posedge clk)
send_reg_valid<=valid_b;

always @(posedge clk)
if(valid_b)
begin
    if(counter_a>=12'd1&&counter_a<=12'd16)send_reg<=send_rega[counter_a-1];
    else if(counter_a>=12'd17&&counter_a<=last_rev_addr+17)send_reg<=rev_data;
    else send_reg<=check_sum;
end

reg valid_b;

reg EPCS_EN_d1,EPCS_EN_d2;

always @(posedge clk)
begin

    EPCS_EN_d1<=EPCS_EN;
    EPCS_EN_d2<=EPCS_EN_d1;
    
end

reg rev_valid_d1,rev_valid_d2;
always @(posedge clk)
begin
    rev_valid_d1<=rev_valid;
    rev_valid_d2<=rev_valid_d1;
end

reg correct_valid_t;
always @(posedge clk)
begin
   if(reset)correct_valid_t<=1'b0;
    else if(EPCS_EN_d2&&rev_valid_d1&&!rev_valid_d2)correct_valid_t<=1'b1;
    else if(!EPCS_EN_d2&&correct_valid)correct_valid_t<=1'b1;
    else if(counter_a==1)correct_valid_t<=1'b0;
end

reg mybusy;
always @(posedge clk)
begin
if(reset)mybusy<=1'b0;
else if(correct_valid_t&&!mybusy) mybusy<=1'b1;
else if(counter_a==0)//(mytime==20'd1000000)
 mybusy<=1'b0;

end
reg mywait_en;
reg [19:0] mytime;
always @(posedge clk)
begin
    if(counter_a==last_rev_addr+18)begin mywait_en<=1'b1;mytime<=20'd0;end
    else if(mywait_en)
        begin
            if(mytime<20'd1000000)mytime<=mytime+1'b1;
            else begin mytime<=0;mywait_en<=1'b0;end
        end
    else begin mytime<=0;mywait_en<=1'b0;end

end

always @(posedge clk)
begin
//if(EPCS_EN_d2&&rev_valid_d1&&!rev_valid_d2&&!mybusy)
if(correct_valid_t&&!mybusy)
    begin
        counter_a<=12'd1;valid_a<=1'b0;valid_b<=1'b0;
    end
//else if(!EPCS_EN_d2&&correct_valid&&!mybusy)begin counter_a<=12'd1;valid_a<=1'b0;valid_b<=1'b0;end
else if(valid_a)
    begin
        valid_a<=1'b0;
        valid_b<=1'b1;
        
    end
else if(valid_b)
    begin
        valid_b<=1'b0;
        if(counter_a<last_rev_addr+18)counter_a<=counter_a+1'b1;
        else counter_a<=12'd0;
    end        
    
else if(mystate==idle)
    begin
        if(counter_a>=12'd1&&counter_a<=last_rev_addr+18)valid_a<=1'b1;
        else valid_a<=1'b0;
    end


        
end



always @(posedge clk)
if(rden)begin rden<=1'b0;raddr<=11'd0;end
else if(mystate==idle)
    begin
        if(counter_a>=12'd17&&counter_a<=last_rev_addr+17)begin rden<=1'b1;raddr<=counter_a-17;end
        else rden<=1'b0;
    end
else begin rden<=1'b0;raddr<=11'd0;end

always @(posedge clk)
begin
    if(counter_a>=12'd4&&counter_a<=last_rev_addr+17)
        begin
            check_valid<=1'b1;
        end
    else
        check_valid<=1'b0;
end
//always @(posedge clk)
//begin
//if(valid)                    begin valid_a<=1'b1;send_rega<=rx_dout;end
//else if(mystate==idle)    begin valid_a<=1'b0;send_reg<=send_rega; end
//end












reg valid_c,valid_d;







always @(posedge clk)
begin
    if(cnt<4'd15)begin reset<=1'b1;cnt<=cnt+1'b1;end
    else begin reset<=1'b0;end
end

reg [3:0]i;
always @(posedge clk)
begin
    if(reset)mystate<=idle;
    else
        begin
            case(mystate)
                idle:
                    begin
                        if(valid_a)         begin mystate<=send;i<=0;end
                        //else if(valid_c)begin mystate<=send_t;i<=0;end
                        else mystate<=idle;
                    end
                send:
                    begin
                        if(i<10)
                            begin
                                if(counter<baud_sample_num-1)begin counter<=counter+1'b1;end
                                else begin counter<=0;i<=i+1;end
                            end
                        else
                            begin
                                if(counter<baud_sample_num-1)begin counter<=counter+1'b1;end
                                else begin counter<=0;i<=0;mystate<=idle;end
                            end
                     end
//                send_t:
//                    begin
//                        if(i<10)
//                            begin
//                                if(counter<baud_sample_num-1)begin counter<=counter+1'b1;end
//                                else begin counter<=0;i<=i+1;end
//                            end
//                        else
//                            begin
//                                if(counter<baud_sample_num-1)begin counter<=counter+1'b1;end
//                                else begin counter<=0;i<=0;mystate<=idle;end
//                            end
//                     end
                    
                 default:mystate<=idle;
                endcase
            end
end
 always @(posedge clk)
begin
    if(mystate==send)
        begin
            if(i==0)txd<=1'b0;
            else if(i==9||i==10)txd<=1'b1;
            else txd<=send_reg[i-1];
        end
//    else if(mystate==send_t)
//        begin
//            if(i==0)txd<=1'b0;
//            else if(i==9||i==10)txd<=1'b1;
//            else txd<=send_regl[i-1];
//        end
     else txd<=1'b1;
end

endmodule