1 /********************************************************************************* 2 * Company : 3 * Engineer : 空气微凉 4 * 5 * Create Date : 00:00:00 22/03/2013 6 * Design Name : 7 * Module Name : 8 * Project Name : 9 * Target Devices : 10 * Tool versions : 11 * Description : 12 * http://www.cnblogs.com/kongqiweiliang/ 13 * Dependencies : 14 * 15 * Revision : 16 * Revision : 0.01 - File Created 17 * Additional Comments : 基础实验_13_有限状态机 ：Mealy型序列检测器 18 ********************************************************************************/ 19 `timescale 1ns/1ps 20 `define UD #1 21 /*******************************************************************************/ 22 module SEQ_REC_MEALY 23 ( 24 //system interface 25 input iCLK_50 ,//50MHz 26 input iRESET ,//system interface 27 //Interface package 28 input iDAT_EN ,// 29 input iDAT ,// 30 output oDAT // 31 ); 32 //------------------------------------------------------------------------------- 33 parameter FSM_IDLE = 3'h0; 34 parameter FSM_0 = 3'h1; 35 parameter FSM_1 = 3'h2; 36 parameter FSM_2 = 3'h3; 37 38 reg [2:0] FSM_CS; 39 reg [2:0] FSM_NS; 40 41 always@(posedge iCLK_50 or negedge iRESET)begin 42 if(!iRESET) 43 FSM_CS <= FSM_IDLE; 44 else 45 FSM_CS <= FSM_NS; 46 end 47 always@(*)begin 48 case(FSM_CS) 49 FSM_IDLE : 50 if(iDAT_EN && iDAT) FSM_NS = FSM_1; 51 else if(iDAT_EN && (!iDAT)) FSM_NS = FSM_0; 52 else FSM_NS = FSM_IDLE; 53 FSM_0 : 54 if(!iDAT) FSM_NS = FSM_0; 55 else if(iDAT) FSM_NS = FSM_1; 56 else FSM_NS = FSM_IDLE; 57 FSM_1 : 58 if(!iDAT) FSM_NS = FSM_0; 59 else if(iDAT) FSM_NS = FSM_2; 60 else FSM_NS = FSM_IDLE; 61 FSM_2 : 62 if(!iDAT) FSM_NS = FSM_0; 63 else if(iDAT) FSM_NS = FSM_2; 64 else FSM_NS = FSM_IDLE; 65 default : 66 FSM_NS = FSM_IDLE; 67 endcase 68 end 69 70 assign oDAT = ((FSM_CS == FSM_2) && iDAT) ? 1'h1 : 1'h0; 71 //------------------------------------------------------------------------------- 72 endmodule