每天进步一点点------任意整数分频，占空比50%

/*********************************************************************************
* Company                    : 
* Engineer                    :     绌烘皵寰�噳
* 
* Create Date                :     00:00:00 22/03/2013 
* Design Name                : 
* Module Name                :         
* Project Name                :  
* Target Devices            : 
* Tool versions            : 
* Description                :  
*                                   http://www.cnblogs.com/kongqiweiliang/             
* Dependencies                : 
*
* Revision                    : 
* Revision                    :     0.01 - File Created
* Additional Comments    : 
********************************************************************************/
`timescale 1ns/100ps
`define    UD  #1
/****************************任意整数分频模块,占空比50%****************************/
module Int_DIV  
(
    input                             iCLK                ,//输入时钟
    output                             oCLK_DIV             //输出时钟
);
//参数--分频系数
parameter F_DIV = 6              ; //分频系数<<<<-----修改这里
parameter F_DIV_WIDTH = 32     ;//分频计数器宽度

reg    [F_DIV_WIDTH - 1:0]        timer_p,timer_n;/* 上升、下降沿脉冲计数器 */
reg    clock_p,clock_n;/* 上升、下降沿脉冲 */

always @(posedge iCLK)begin/* 上升沿脉冲计数器 */
    if(timer_p < F_DIV - 1'b1)
        timer_p <= timer_p + 1'b1;
    else
        timer_p <= 0;
end

always @(negedge iCLK)begin/* 下降沿脉冲计数器 */
    if(timer_n < F_DIV - 1'b1)
        timer_n <= timer_n + 1'b1;
    else
        timer_n <= 0;
end

always @(posedge iCLK)begin/* 上升沿脉冲 */
    if(timer_p == (F_DIV>>1) - 1'b1)
        clock_p <= 1'b0;
    else if(timer_p == F_DIV - 1'b1)
        clock_p <= 1'b1;
end

always @(negedge iCLK)begin/* 下降沿脉冲 */
    if(timer_n == (F_DIV>>1) - 1'b1)
        clock_n <= 1'b0;
    else if(timer_n == F_DIV - 1'b1)
        clock_n <= 1'b1;
end

assign oCLK_DIV = (F_DIV[0] == 1) ? (clock_p | clock_n) : clock_p;

endmodule