1 /********************************************************************************* 2 * Company : 3 * Engineer : 绌烘皵寰�噳 4 * 5 * Create Date : 00:00:00 22/03/2013 6 * Design Name : 7 * Module Name : 8 * Project Name : 9 * Target Devices : 10 * Tool versions : 11 * Description : 12 * http://www.cnblogs.com/kongqiweiliang/ 13 * Dependencies : 14 * 15 * Revision : 16 * Revision : 0.01 - File Created 17 * Additional Comments : 18 ********************************************************************************/ 19 `timescale 1ns/100ps 20 `define UD #1 21 /****************************任意整数分频模块,占空比50%****************************/ 22 module Int_DIV 23 ( 24 input iCLK ,//输入时钟 25 output oCLK_DIV //输出时钟 26 ); 27 //参数--分频系数 28 parameter F_DIV = 6 ; //分频系数<<<<-----修改这里 29 parameter F_DIV_WIDTH = 32 ;//分频计数器宽度 30 31 reg [F_DIV_WIDTH - 1:0] timer_p,timer_n;/* 上升、下降沿脉冲计数器 */ 32 reg clock_p,clock_n;/* 上升、下降沿脉冲 */ 33 34 always @(posedge iCLK)begin/* 上升沿脉冲计数器 */ 35 if(timer_p < F_DIV - 1'b1) 36 timer_p <= timer_p + 1'b1; 37 else 38 timer_p <= 0; 39 end 40 41 always @(negedge iCLK)begin/* 下降沿脉冲计数器 */ 42 if(timer_n < F_DIV - 1'b1) 43 timer_n <= timer_n + 1'b1; 44 else 45 timer_n <= 0; 46 end 47 48 always @(posedge iCLK)begin/* 上升沿脉冲 */ 49 if(timer_p == (F_DIV>>1) - 1'b1) 50 clock_p <= 1'b0; 51 else if(timer_p == F_DIV - 1'b1) 52 clock_p <= 1'b1; 53 end 54 55 always @(negedge iCLK)begin/* 下降沿脉冲 */ 56 if(timer_n == (F_DIV>>1) - 1'b1) 57 clock_n <= 1'b0; 58 else if(timer_n == F_DIV - 1'b1) 59 clock_n <= 1'b1; 60 end 61 62 assign oCLK_DIV = (F_DIV[0] == 1) ? (clock_p | clock_n) : clock_p; 63 64 endmodule