Quartus宏模块的应用lpm_ram_dp（双端口ram）

Altera官网提供的时序图：

Altera官网提供的模块：

仿真程序：

`timescale 1ns/1ns
`define clk_cycle 5
module testbench;
reg [15:0]data;
reg [6:0]wraddress;
reg  wren;
reg [6:0]rdaddress;
reg rden;
reg wrclock;
reg rdclock;

reg clk_sys;
wire [15:0]q;
always #`clk_cycle clk_sys=~clk_sys;

initial 
begin
data=0;
wraddress=0;
wren=0;
rdaddress=0;
rden=0;
wrclock=0;
rdclock=0;
clk_sys=0;
end

always @(posedge clk_sys)
begin
    wrclock<=~wrclock;
end

always @(negedge clk_sys)
begin
    if(wrclock==0)
        begin
        if(wraddress==10)
            begin
            wren<=0;
            rden<=1;
            end
        else
            begin
            wren<=1;
            rden<=0;
            wraddress<=wraddress+1;
            data<=data+1;
            end
        end
    else
        begin
        wraddress<=wraddress;
        data<=data;
        end
end

always @(posedge clk_sys)
begin
    rdclock<=~rdclock;
end

always @(negedge rdclock)
begin
    if(rden==1)
    begin
    if(rdaddress==10)
        begin
        rden=0;    
        end
    else
        rdaddress<=rdaddress+1;
    end
end
DspBus m0(.wren(wren),.rden(rden),.wrclock(wrclock),
          .rdclock(rdclock),.data(data),.rdaddress(rdaddress),
          .wraddress(wraddress),.q(q));

endmodule