1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * This file contains the configuration parameters for the RT2880 board. 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 //#define DEBUG 1 32 //#define ET_DEBUG 33 #define CONFIG_RT2880_ETH 1 /* Enable built-in 10/100 Ethernet */ 34 35 #define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ 36 //CONFIG_INCA_IP 37 #if defined (RT3052_FPGA_BOARD) || defined (RT3352_FPGA_BOARD) || \ 38 defined (RT2883_FPGA_BOARD) || defined (RT3883_FPGA_BOARD) || \ 39 defined (RT5350_FPGA_BOARD) || defined (RT6855_FPGA_BOARD) || \ 40 defined (MT7620_FPGA_BOARD) || defined (MT7621_FPGA_BOARD) || \ 41 defined (RT6855A_FPGA_BOARD) 42 #define FPGA_BOARD_CLOCK_RATE 40000000 43 #else 44 #define FPGA_BOARD_CLOCK_RATE 25000000 45 #endif 46 #define PALMCHIP_CLOCK_DIVISOR 16 47 #define FPGA_BOARD_CLOCK_DIVISOR 32 48 49 /* allowed values: 100000000, 133000000, and 150000000 */ 50 #if 1 /* for CFG_HZ only */ 51 52 #ifdef RT2880_ASIC_BOARD 53 #define CPU_CLOCK_RATE 266666666 /* default: 150 MHz clock for the MIPS core */ 54 #elif defined (RT3052_ASIC_BOARD) 55 #define CPU_CLOCK_RATE 384000000 56 #elif defined (RT3352_ASIC_BOARD) 57 #define CPU_CLOCK_RATE 400000000 58 #elif defined (RT6855_ASIC_BOARD) || defined (RT6855A_ASIC_BOARD) 59 #define CPU_CLOCK_RATE 500000000 60 #elif defined (MT7620_ASIC_BOARD) 61 #define CPU_CLOCK_RATE 600000000 62 #elif defined (MT7621_ASIC_BOARD) 63 #define CPU_CLOCK_RATE 400000000 64 #elif defined (RT2883_ASIC_BOARD) 65 #define CPU_CLOCK_RATE 400000000 66 #elif defined (RT3883_ASIC_BOARD) 67 #define CPU_CLOCK_RATE 500000000 68 #elif defined (RT5350_ASIC_BOARD) 69 #define CPU_CLOCK_RATE 360000000 70 #else 71 #define CPU_CLOCK_RATE FPGA_BOARD_CLOCK_RATE /* default: 150 MHz clock for the MIPS core */ 72 #endif 73 74 #endif 75 76 #define SERIAL_CLOCK_DIVISOR 16 77 78 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 79 80 #define CONFIG_BAUDRATE 57600 81 82 #define CONFIG_SERVERIP 192.168.120.36 83 #define CONFIG_IPADDR 192.168.120.123 84 #define CONFIG_ETHADDR "00:AA:BB:CC:DD:10" 85 /* valid baudrates */ 86 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 87 88 //#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 89 90 #undef CONFIG_BOOTARGS 91 //#define CONFIG_BOOTARGS 92 93 #define CONFIG_BOOTCOMMAND "tftp" //"run flash_self" 94 95 96 #include <cmd_confdefs.h> 97 98 /* 99 * Miscellaneous configurable options 100 */ 101 #define CFG_LONGHELP /* undef to save memory */ 102 103 #if defined (RT2880_FPGA_BOARD) || defined (RT2880_ASIC_BOARD) 104 #define CFG_PROMPT "RT2880 # " 105 #elif defined (RT2883_FPGA_BOARD) || defined (RT2883_ASIC_BOARD) 106 #define CFG_PROMPT "RT2883 # " 107 #elif defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) 108 #define CFG_PROMPT "RT3052 # " 109 #elif defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) 110 #define CFG_PROMPT "RT3352 # " 111 #elif defined (RT3883_FPGA_BOARD) || defined (RT3883_ASIC_BOARD) 112 #define CFG_PROMPT "RT3883 # " 113 #elif defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD) 114 #define CFG_PROMPT "RT5350 # " 115 #elif defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD) 116 #define CFG_PROMPT "RT6855 # " 117 #elif defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD) 118 #define CFG_PROMPT "RT6855A # " 119 #elif defined (MT7620_FPGA_BOARD) || defined (MT7620_ASIC_BOARD) 120 #define CFG_PROMPT "MT7620 # " 121 #elif defined (MT7621_FPGA_BOARD) || defined (MT7621_ASIC_BOARD) 122 #define CFG_PROMPT "MT7621 # " 123 #else 124 #define CFG_PROMPT "RTxxxx # " 125 #endif 126 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 127 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 128 #define CFG_MAXARGS 16 /* max number of command args*/ 129 130 #define CFG_MALLOC_LEN 256*1024 131 132 #define CFG_BOOTPARAMS_LEN 128*1024 133 134 #define CFG_HZ CPU_CLOCK_RATE/2 135 136 #if defined (RT2880_FPGA_BOARD) || defined (RT2880_ASIC_BOARD) 137 #define CFG_SDRAM_BASE 0x8A000000 138 #else 139 #define CFG_SDRAM_BASE 0x80000000 140 #endif 141 142 143 /* 144 * for TEST 145 */ 146 #define CFG_CONSOLE_INFO_QUIET 147 148 #if defined (RT2880_FPGA_BOARD) || defined (RT2880_ASIC_BOARD) 149 #define CFG_LOAD_ADDR 0x8A100000 /* default load address */ 150 #define CFG_HTTP_DL_ADDR 0x8A300000 151 152 #define CFG_MEMTEST_START 0x8A100000 153 #define CFG_MEMTEST_END 0x8A400000 154 #else 155 #define CFG_LOAD_ADDR 0x80100000 /* default load address */ 156 #define CFG_HTTP_DL_ADDR 0x80300000 157 #if defined(RT6855A_FPGA_BOARD) || defined(RT6855A_ASIC_BOARD) || defined(MT7620_FPGA_BOARD) || defined(MT7620_ASIC_BOARD) 158 #define CFG_SPINAND_LOAD_ADDR 0x80c00000 159 #else 160 #define CFG_SPINAND_LOAD_ADDR 0x80500000 161 #endif 162 163 #define CFG_MEMTEST_START 0x80100000 164 #define CFG_MEMTEST_END 0x80400000 165 #endif 166 167 168 #define CFG_EMBEDED_SRAM_START 0xA0800000 169 #define CFG_EMBEDED_SRAM_FOR_RXRING0_DESC 0xA0800000 170 #define CFG_EMBEDED_SRAM_FOR_TXRING0_DESC 0xA0800100 171 #define CFG_EMBEDED_SRAM_FOR_TXRING1_DESC 0xA0800200 172 #define CFG_EMBEDED_SRAM_BUF_START 0xA0800300 173 #define CFG_EMBEDED_SRAM_SDP0_BUF_START 0xA0804000 174 #define CFG_EMBEDED_SRAM_END 0xA0807FFF 175 176 /*----------------------------------------------------------------------- 177 * FLASH and environment organization 178 */ 179 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 180 #define CFG_MAX_FLASH_SECT (263) /* max number of sectors on one chip */ 181 182 #if defined (RT2880_FPGA_BOARD) || defined (RT2880_ASIC_BOARD) 183 #ifdef DUAL_IMAGE_SUPPORT 184 #define PHYS_FLASH_START 0xBC000000 /* Address for issuing flash command */ 185 #if defined (ON_BOARD_2M_FLASH_COMPONENT) 186 #define PHYS_FLASH_1 0xBC000000 /* Image1 Bank #1 */ 187 #define PHYS_FLASH2_1 0xBC100000 /* Image2 Bank #1 */ 188 #elif defined (ON_BOARD_4M_FLASH_COMPONENT) 189 #define PHYS_FLASH_1 0xBC000000 /* Image1 Bank #1 */ 190 #define PHYS_FLASH2_1 0xBC200000 /* Image2 Bank #1 */ 191 #elif defined (ON_BOARD_8M_FLASH_COMPONENT) 192 #define PHYS_FLASH_1 0xBC400000 /* Image1 Bank #1 */ 193 #define PHYS_FLASH_2 0xBC000000 /* Image1 Bank #2 */ 194 #define PHYS_FLASH2_1 0xBC000000 /* Image2 Bank #1 */ 195 #elif defined (ON_BOARD_16M_FLASH_COMPONENT) 196 #define PHYS_FLASH_1 0xBCC00000 /* Image1 Bank #1 */ 197 #define PHYS_FLASH_2 0xBC000000 /* Image1 Bank #2 */ 198 #define PHYS_FLASH2_1 0xBC400000 /* Image2 Bank #1 */ 199 #define PHYS_FLASH2_2 0xBC800000 /* Image2 Bank #2 */ 200 #endif 201 #else //Non Dual Image 202 #ifdef ON_BOARD_8M_FLASH_COMPONENT 203 #define PHYS_FLASH_1 0xBC400000 /* Flash Bank #1 */ 204 #else 205 #define PHYS_FLASH_1 0xBCC00000 /* Flash Bank #1 */ 206 #endif 207 #define PHYS_FLASH_2 0xBC000000 /* Flash Bank #2 */ 208 #if defined (ON_BOARD_8M_FLASH_COMPONENT) || defined (ON_BOARD_16M_FLASH_COMPONENT) 209 #define PHYS_FLASH_START PHYS_FLASH_2 /* Address for issuing flash command */ 210 #else 211 #define PHYS_FLASH_START PHYS_FLASH_1 /* Address for issuing flash command */ 212 #endif 213 #endif 214 #elif defined (RT2883_FPGA_BOARD) || defined (RT2883_ASIC_BOARD) || \ 215 defined (RT3883_FPGA_BOARD) || defined (RT3883_ASIC_BOARD) || \ 216 defined (RT3352_FPGA_BOARD) || defined (RT3352_ASIC_BOARD) || \ 217 defined (RT5350_FPGA_BOARD) || defined (RT5350_ASIC_BOARD) || \ 218 defined (RT6855_FPGA_BOARD) || defined (RT6855_ASIC_BOARD) || \ 219 defined (MT7620_FPGA_BOARD) || defined (MT7620_ASIC_BOARD) || \ 220 defined (MT7621_FPGA_BOARD) || defined (MT7621_ASIC_BOARD) 221 #define PHYS_FLASH_START 0xBC000000 /* Flash Bank #2 */ 222 #define PHYS_FLASH_1 0xBC000000 /* Flash Bank #1 */ 223 #ifdef DUAL_IMAGE_SUPPORT 224 #if defined (ON_BOARD_2M_FLASH_COMPONENT) 225 #define PHYS_FLASH2_1 0xBC100000 /* Flash Bank #2 */ 226 #elif defined (ON_BOARD_4M_FLASH_COMPONENT) 227 #define PHYS_FLASH2_1 0xBC200000 /* Flash Bank #2 */ 228 #elif defined (ON_BOARD_8M_FLASH_COMPONENT) 229 #define PHYS_FLASH2_1 0xBC400000 /* Flash Bank #2 */ 230 #elif defined (ON_BOARD_16M_FLASH_COMPONENT) 231 #define PHYS_FLASH2_1 0xBC800000 /* Flash Bank #2 */ 232 #elif defined (ON_BOARD_32M_FLASH_COMPONENT) 233 #define PHYS_FLASH2_1 0xBD000000 /* Flash Bank #2 */ 234 #endif 235 #endif // DUAL_IMAGE_SUPPORT 236 #elif defined (RT3052_FPGA_BOARD) || defined (RT3052_ASIC_BOARD) 237 // RT3052_MP2 and 32M_FLASH 238 #define PHYS_FLASH_START 0xBF000000 /* Address for issuing flash command */ 239 #define PHYS_FLASH_1 0xBF000000 /* Flash Bank #1 */ 240 #ifdef DUAL_IMAGE_SUPPORT 241 #if defined (ON_BOARD_2M_FLASH_COMPONENT) 242 #define PHYS_FLASH2_1 0xBF100000 /* Flash Bank #2 */ 243 #elif defined (ON_BOARD_4M_FLASH_COMPONENT) 244 #define PHYS_FLASH2_1 0xBF200000 /* Flash Bank #2 */ 245 #elif defined (ON_BOARD_8M_FLASH_COMPONENT) 246 #define PHYS_FLASH2_1 0xBF400000 /* Flash Bank #2 */ 247 #elif defined (ON_BOARD_16M_FLASH_COMPONENT) 248 #define PHYS_FLASH2_1 0xBF800000 /* Flash Bank #2 */ 249 #elif defined (ON_BOARD_32M_FLASH_COMPONENT) 250 #define PHYS_FLASH2_1 0xBB000000 /* Flash Bank #2 */ 251 #undef CFG_MAX_FLASH_BANKS 252 #define CFG_MAX_FLASH_BANKS 2 253 #endif 254 //#define PHYS_FLASH_2 0xBF000000 /* Flash Bank #2 */ 255 #else // Non Dual Image 256 #ifdef ON_BOARD_32M_FLASH_COMPONENT 257 #define PHYS_FLASH2_START 0xBB000000 /* Flash Bank #2 */ 258 #define PHYS_FLASH_2 0xBB000000 /* Flash Bank #2 */ 259 #undef CFG_MAX_FLASH_BANKS 260 #define CFG_MAX_FLASH_BANKS 2 261 #endif 262 #endif 263 #elif defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD) 264 #define PHYS_FLASH_1 0xB0000000 265 #endif // defined (RT2880_FPGA_BOARD) || defined (RT2880_ASIC_BOARD) 266 267 /* The following #defines are needed to get flash environment right */ 268 #define CFG_MONITOR_BASE TEXT_BASE 269 270 #define CFG_MONITOR_LEN (192 << 10) 271 272 #define CFG_INIT_SP_OFFSET 0x400000 273 274 #define CFG_FLASH_BASE PHYS_FLASH_1 275 #ifdef DUAL_IMAGE_SUPPORT 276 #define CFG_FLASH2_BASE PHYS_FLASH2_1 277 #endif 278 279 /* timeout values are in ticks */ 280 #define CFG_FLASH_ERASE_TOUT (15UL * CFG_HZ) /* Timeout for Flash Erase */ 281 #define CFG_FLASH_WRITE_TOUT (5 * CFG_HZ) /* Timeout for Flash Write */ 282 #define CFG_ETH_AN_TOUT (5 * CFG_HZ) /* Timeout for Flash Write */ 283 #define CFG_ETH_LINK_UP_TOUT (5 * CFG_HZ) /* Timeout for Flash Write */ 284 #define CFG_FLASH_STATE_DISPLAY_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */ 285 286 #if defined (ON_BOARD_32M_FLASH_COMPONENT) && !defined (DUAL_IMAGE_SUPPORT) 287 #define CFG_BOOTLOADER_SIZE 0x40000 288 #define CFG_CONFIG_SIZE 0x20000 289 #define CFG_FACTORY_SIZE 0x20000 290 #define CFG_ENV_ADDR (PHYS_FLASH_2 + 0x1000000 - CFG_BOOTLOADER_SIZE) 291 #define CFG_FACTORY_ADDR (PHYS_FLASH_2 + 0x1000000 - CFG_FACTORY_SIZE) 292 #define CFG_KERN_ADDR (CFG_FLASH_BASE + CFG_BOOTLOADER_SIZE) 293 #define CFG_KERN2_ADDR (CFG_FLASH2_BASE + CFG_BOOTLOADER_SIZE) 294 #else 295 #if defined(SMALL_UBOOT_PARTITION) 296 #define CFG_BOOTLOADER_SIZE 0x20000 297 #define CFG_CONFIG_SIZE 0x10000 298 #define CFG_FACTORY_SIZE 0x00000 299 #else 300 #define CFG_BOOTLOADER_SIZE 0x30000 301 #define CFG_CONFIG_SIZE 0x10000 302 #define CFG_FACTORY_SIZE 0x10000 303 #endif 304 305 #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_BOOTLOADER_SIZE) 306 #define CFG_FACTORY_ADDR (CFG_FLASH_BASE + CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE) 307 #define CFG_KERN_ADDR (CFG_FLASH_BASE + (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE)) 308 #ifdef DUAL_IMAGE_SUPPORT 309 #define CFG_KERN2_ADDR (CFG_FLASH2_BASE + (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE)) 310 #endif 311 #endif 312 313 #define CFG_ENV_SECT_SIZE CFG_CONFIG_SIZE 314 #define CFG_ENV_SIZE 0x1000 315 316 #if defined(SMALL_UBOOT_PARTITION) 317 #define CFG_UBOOT_SECT_SIZE CFG_BOOTLOADER_SIZE 318 #define CFG_UBOOT_SIZE 0x19000 // must <= CFG_FACTORY_ADDR 319 #define CFG_RF_PARAM_SIZE 0x800 320 #undef CFG_FACTORY_ADDR 321 #define CFG_FACTORY_ADDR (CFG_BOOTLOADER_SIZE - (2 * CFG_RF_PARAM_SIZE)) 322 #define CFG_FACTORY_ADDR2 (CFG_BOOTLOADER_SIZE - CFG_RF_PARAM_SIZE) 323 #endif 324 325 #if defined (DUAL_IMAGE_SUPPORT) 326 #if defined (ON_BOARD_2M_FLASH_COMPONENT) 327 #define CFG_KERN_SIZE (0x100000 - (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE)) 328 #elif defined (ON_BOARD_4M_FLASH_COMPONENT) 329 #define CFG_KERN_SIZE (0x200000 - (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE)) 330 #elif defined (ON_BOARD_8M_FLASH_COMPONENT) 331 #define CFG_KERN_SIZE (0x400000 - (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE)) 332 #elif defined (ON_BOARD_16M_FLASH_COMPONENT) 333 #define CFG_KERN_SIZE (0x800000 - (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE)) 334 #endif 335 #define CFG_KERN2_SIZE CFG_KERN_SIZE 336 #else // Non Dual Image 337 #if defined (ON_BOARD_2M_FLASH_COMPONENT) 338 #define CFG_KERN_SIZE (0x200000 - (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE)) 339 #elif defined (ON_BOARD_4M_FLASH_COMPONENT) 340 #define CFG_KERN_SIZE (0x400000 - (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE)) 341 #elif defined (ON_BOARD_8M_FLASH_COMPONENT) 342 #define CFG_KERN_SIZE (0x800000 - (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE)) 343 #elif defined (ON_BOARD_16M_FLASH_COMPONENT) 344 #define CFG_KERN_SIZE (0x1000000 - (CFG_BOOTLOADER_SIZE + CFG_CONFIG_SIZE + CFG_FACTORY_SIZE)) 345 #endif 346 #endif 347 348 #define CONFIG_FLASH_16BIT 349 350 #define CONFIG_NR_DRAM_BANKS 1 351 //#define CONFIG_NET_MULTI 352 #define CFG_RX_ETH_BUFFER 60 353 354 /*----------------------------------------------------------------------- 355 * Cache Configuration 356 */ 357 #define CFG_DCACHE_SIZE (16*1024) 358 #define CFG_ICACHE_SIZE (16*1024) 359 #define CFG_CACHELINE_SIZE 16 360 361 #define RT2880_REGS_BASE 0xA0000000 362 #define CONFIG_AUTO_COMPLETE 363 364 365 /* 366 * System Controller (0x00300000) 367 * Offset 368 * 0x10 -- SYSCFG System Configuration Register 369 * 0x30 -- CLKCFG1 Clock Configuration Register 370 * 0x34 -- RSTCTRL Reset Control Register 371 * 0x38 -- RSTSTAT Reset Status Register 372 * 0x60 -- GPIOMODE GPIO Mode Control Register 373 */ 374 #define RT2880_SYS_CNTL_BASE (RALINK_SYSCTL_BASE) 375 #if defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD) 376 #define RT2880_SYSCFG_REG (RT2880_SYS_CNTL_BASE+0x8c) 377 #define RT2880_RSTCTRL_REG (RT2880_SYS_CNTL_BASE+0x834) 378 #define RT2880_RSTSTAT_REG (RT2880_SYS_CNTL_BASE+0x38) 379 #define RT2880_GPIOMODE_REG (RT2880_SYS_CNTL_BASE+0x860) 380 #else 381 #define RT2880_SYSCFG_REG (RT2880_SYS_CNTL_BASE+0x10) 382 #define RT2880_SYSCFG1_REG (RT2880_SYS_CNTL_BASE+0x14) 383 #define RT2880_CLKCFG1_REG (RT2880_SYS_CNTL_BASE+0x30) 384 #define RT2880_RSTCTRL_REG (RT2880_SYS_CNTL_BASE+0x34) 385 #define RT2880_RSTSTAT_REG (RT2880_SYS_CNTL_BASE+0x38) 386 #define RT2880_SYSCLKCFG_REG (RT2880_SYS_CNTL_BASE+0x3c) 387 #define RT2880_GPIOMODE_REG (RT2880_SYS_CNTL_BASE+0x60) 388 #endif 389 390 #define RT2880_PRGIO_ADDR (RALINK_SYSCTL_BASE + 0x600) // Programmable I/O 391 #define RT2880_REG_PIOINT (RT2880_PRGIO_ADDR + 0) 392 #define RT2880_REG_PIOEDGE (RT2880_PRGIO_ADDR + 0x04) 393 #define RT2880_REG_PIORENA (RT2880_PRGIO_ADDR + 0x08) 394 #define RT2880_REG_PIOFENA (RT2880_PRGIO_ADDR + 0x0C) 395 #define RT2880_REG_PIODATA (RT2880_PRGIO_ADDR + 0x20) 396 #define RT2880_REG_PIODIR (RT2880_PRGIO_ADDR + 0x24) 397 398 #define RALINK_REG(x) (*((volatile u32 *)(x))) 399 #if defined (RT6855A_FPGA_BOARD) || defined (RT6855A_ASIC_BOARD) 400 #define ra_inb(offset) (*(volatile unsigned char *)(offset)) 401 #define ra_inw(offset) (*(volatile unsigned short *)(offset)) 402 #define ra_inl(offset) (*(volatile unsigned long *)(offset)) 403 404 #define ra_outb(offset,val) (*(volatile unsigned char *)(offset) = val) 405 #define ra_outw(offset,val) (*(volatile unsigned short *)(offset) = val) 406 #define ra_outl(offset,val) (*(volatile unsigned long *)(offset) = val) 407 408 #define ra_and(addr, value) ra_outl(addr, (ra_inl(addr) & (value))) 409 #define ra_or(addr, value) ra_outl(addr, (ra_inl(addr) | (value))) 410 #endif 411 #define RT2880_WDRST (1<<1) 412 #define RT2880_SWSYSRST (1<<2) 413 #define RT2880_SWCPURST (1<<3) 414 415 416 #define RT2880_UPHY0_CLK_EN (1<<18) 417 #define RT2880_UPHY1_CLK_EN (1<<20) 418 419 420 /* 421 * for USB 422 */ 423 #ifdef RALINK_USB 424 #define CONFIG_USB_OHCI 1 425 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 426 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x101C1000 427 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "rt3680" 428 #define CONFIG_USB_EHCI 1 429 #define CONFIG_USB_STORAGE 1 430 #define CONFIG_DOS_PARTITION 431 #define LITTLEENDIAN 432 #define CONFIG_CRC32_VERIFY 433 #endif /* RALINK_USB */ 434 435 #endif /* __CONFIG_H */