基于verilog的PWM实现

module pwm (clk, write_data, cs, write_n, addr, clr_n, read_data, pwm_out);
input clk;
input [31:0] write_data;

input cs;
input write_n;
input addr;
input clr_n;
output [31:0] read_data;
output pwm_out;
// 定义period和pulse_width寄存器的内容
reg [31:0] period;
reg [31:0] pulse_width;
reg [31:0] counter;
reg off;
reg [31:0] read_data;
wire period_en, pulse_width_en; //写使能


always @(posedge clk or negedge clr_n)
begin
  if (clr_n==0)
  begin
    period<=32&#39;h 00000000;
    pulse_width<=32&#39;h 00000000;
  end
  else begin
    if (period_en) period<=write_data[31:0];
    else period<=period;
    if (pulse_width_en) pulse_width<=write_data[31:0];
    else pulse_width<=pulse_width;
  end
end
// period和pulse_width寄存器的读访问
always @(addr or period or pulse_width)
if (addr == 0) read_data=period;
else read_data=pulse_width;

always @(posedge clk or negedge clr_n)
begin
  if (clr_n==0) counter<=0;
  else if (counter>=period-1) counter<=0;
  else counter<=counter+1;
end

always @(posedge clk or negedge clr_n)
begin
  if (clr_n==0) off<=0;  
  else if (counter>=pulse_width) off <= 1;
  else if (counter==0)   off<=0;
  else off<=off;
end

assign period_en = cs & !write_n & !addr;
assign pulse_width_en = cs & !write_n & addr;

endmodule