module lxl(clk,rst,led,sel,dig);
input clk,rst;
output reg [7:0] led;
output reg [5:0] sel;
output [7:0] dig;
parameter s1=1'b0,s2=1'b1;
reg current_state,next_state;
parameter T1s=31'd2_0000_000;
reg [4:0] t;
reg [31:0] cnt,cnt1;
wire w;
reg clk_out;
always @ (posedge clk or negedge rst)
if(!rst)
begin
cnt<=0;
t<=0;
end
else if(cnt==T1s)
begin
cnt<=0;
t<=t+1;
//if(t==5)
// t<=0;
end
else
begin
cnt<=cnt+1;
if(t==9)
t<=0;
end
assign w=(t==9)?1'b1:1'b0;
always @(posedge clk or negedge rst)
if(!rst)
clk_out<=0;
else if(cnt1==(T1s/100))
begin
cnt1<=0;
clk_out<=~clk_out;
end
else
cnt1<=cnt1+1;
always @ (posedge clk or negedge rst)
if(!rst)
sel<=8'hff;
else if(clk_out)
sel<=8'h1f;
else
sel<=8'h3e;
always @ (posedge clk or negedge rst)
if(!rst)
current_state<=s1;
else
current_state<=next_state;
always @ (w or current_state)
begin
next_state<=s1;
case(current_state)
s1:if(w) next_state<=s2;else next_state<=s1;
s2:if(w) next_state<=s1;else next_state<=s2;
default: next_state<=1'bz;
endcase
end
always @ (current_state)
begin
led<=8'hff;
case(current_state)
//s1:led<=8'hf0;
//s2:led<=8'h0f;
s1:begin led[0]<=1;led[7]<=0;if(clk_out) ledon(t,dig);if(t<5) begin led[1]<=0;led[2]<=1;
if(~clk_out) ledon(t,dig);end
else begin led[1]<=1;led[2]<=0;if(~clk_out) ledon(t-5,dig);end end
s2:begin led[7]<=1;led[0]<=0;if(~clk_out) ledon(t,dig);if(t<5) begin led[5]<=1;led[6]<=0;
if(clk_out) ledon(t,dig);end
else begin led[5]<=0;led[6]<=1;if(clk_out) ledon(t-5,dig);end end
default: led<=8'hzz;
endcase
end
task ledon;
input [7:0] duan;
output [7:0] du;
case(duan)
0: du=8'hc0;
1: du=8'hf9;
2: du=8'ha4;
3: du=8'hb0;
4: du=8'h99;
5: du=8'h92;
6: du=8'h82;
7: du=8'hf8;
8: du=8'h80;
9: du=8'h90;
default: du=8'hff;
endcase
endtask
endmodule