数字系统设计练习（七）—— 简单数码管显示

一、实验硬软件环境：

1. EDA软件：Vivado2019
2. 实验开发板：Basys3 FPGA套件

二、实验内容：

　　实现的电路功能为：本次实验中实现一个简单的数码管显示控制电路，要求四个按键对应4个数码管，当按键1按下， 数码管1显示1；当按键2按下， 数码管2显示2；当按键3按下，数码管3显示3；当按键4按下，数码管显示4；没有按键的时候，数码管同时显示0。

　　数码管的基本原理及实验板数码管对应的管脚配置分别如图所示。

三、 具体实现

1. 设计源码

   `timescale 1ns / 1ps
   //////////////////////////////////////////////////////////////////////////////////
   // Company: 
   // Engineer: 
   // 
   // Create Date: 2020/08/14 20:01:14
   // Design Name: 
   // Module Name: nixietube
   // Project Name: 
   // Target Devices: 
   // Tool Versions: 
   // Description: 
   // 
   // Dependencies: 
   // 
   // Revision:
   // Revision 0.01 - File Created
   // Additional Comments:
   // 
   //////////////////////////////////////////////////////////////////////////////////
   
   
   module nixietube(
       input [3:0] key1,
       output reg [3:0] key2,
       output reg [7:0] out
       );
       
       always @(key1)
       begin
           case(key1)
               4'b0001: 
                   begin
                       key2 = 4'b1110; out = 8'b1001_1110;
                   end
               4'b0010: 
                   begin
                       key2 = 4'b1101; out = 8'b0010_0100;
                   end
               4'b0100: 
                   begin
                       key2 = 4'b1011; out = 8'b0000_1100;
                   end
               4'b1000: 
                   begin
                       key2 = 4'b0111; out = 8'b1001_1000;
                   end
               default: 
                   begin
                       key2 = 4'b0000; out = 8'b0000_0010;
                   end
           endcase
       end
   endmodule

2. 仿真代码

   `timescale 1ns / 1ps
   //////////////////////////////////////////////////////////////////////////////////
   // Company: 
   // Engineer: 
   // 
   // Create Date: 2020/08/15 16:04:31
   // Design Name: 
   // Module Name: nixietube_tb
   // Project Name: 
   // Target Devices: 
   // Tool Versions: 
   // Description: 
   // 
   // Dependencies: 
   // 
   // Revision:
   // Revision 0.01 - File Created
   // Additional Comments:
   // 
   //////////////////////////////////////////////////////////////////////////////////
   
   
   module nixietube_tb;
       reg [3:0] key;
       wire [3:0] switch;
       wire [7:0] out;
       
       nixietube uut(
           .key(key),
           .switch(switch),
           .out(out)
       );
       
       initial
       begin
           key = 4'b0000;
           #100 key = 4'b0001;
           #100 key = 4'b0010;
           #100 key = 4'b0100;
           #100 key = 4'b1000;
           #100;
       end
   endmodule

3. 波形图
4. 约束文件

   set_property PACKAGE_PIN R2 [get_ports key[0]]
   set_property IOSTANDARD LVCMOS33 [get_ports key[0]]
   set_property PACKAGE_PIN T1 [get_ports key[1]]
   set_property IOSTANDARD LVCMOS33 [get_ports key[1]]
   set_property PACKAGE_PIN U1 [get_ports key[2]]
   set_property IOSTANDARD LVCMOS33 [get_ports key[2]]
   set_property PACKAGE_PIN W2 [get_ports key[3]]
   set_property IOSTANDARD LVCMOS33 [get_ports key[3]]
   set_property PACKAGE_PIN W4 [get_ports switch[0]]
   set_property IOSTANDARD LVCMOS33 [get_ports switch[0]]
   set_property PACKAGE_PIN V4 [get_ports switch[1]]
   set_property IOSTANDARD LVCMOS33 [get_ports switch[1]]
   set_property PACKAGE_PIN U4 [get_ports switch[2]]
   set_property IOSTANDARD LVCMOS33 [get_ports switch[2]]
   set_property PACKAGE_PIN U2 [get_ports switch[3]]
   set_property IOSTANDARD LVCMOS33 [get_ports switch[3]]
   set_property PACKAGE_PIN W7 [get_ports out[7]]
   set_property IOSTANDARD LVCMOS33 [get_ports out[7]]
   set_property PACKAGE_PIN W6 [get_ports out[6]]
   set_property IOSTANDARD LVCMOS33 [get_ports out[6]]
   set_property PACKAGE_PIN U8 [get_ports out[5]]
   set_property IOSTANDARD LVCMOS33 [get_ports out[5]]
   set_property PACKAGE_PIN V8 [get_ports out[4]]
   set_property IOSTANDARD LVCMOS33 [get_ports out[4]]
   set_property PACKAGE_PIN U5 [get_ports out[3]]
   set_property IOSTANDARD LVCMOS33 [get_ports out[3]]
   set_property PACKAGE_PIN V5 [get_ports out[2]]
   set_property IOSTANDARD LVCMOS33 [get_ports out[2]]
   set_property PACKAGE_PIN U7 [get_ports out[1]]
   set_property IOSTANDARD LVCMOS33 [get_ports out[1]]
   set_property PACKAGE_PIN V7 [get_ports out[0]]
   set_property IOSTANDARD LVCMOS33 [get_ports out[0]]