vsim - The vsim command invokes the VSIM simulator
-L <library_name> …
(optional) Specifies the library to search for design units instantiated from Verilog and for VHDL default component binding. If multiple libraries are specified, each must be preceded by the -L option.
-t [<multiplier>]<time_unit>
(optional) Specifies the simulator time resolution. <time_unit> must be one of the following:
fs, ps, ns, us, ms, sec
The default is 1ns; the optional <multiplier> may be 1, 10 or 100.
Note that there is no space between the multiplier and the unit (for example, 10fs, not 10 fs).
-assertdebug
keep data for debuging assertion failures.
-debugdb=<db_pathname>
(optional) Instructs Questa SIM to generate a database of connectivity information to be used for post-sim debug in the Dataflow and Schematic windows. The database pathname should have a .dbg extension. If a database pathname is not specified, Questa SIM creates a database file named vsim.dbg in the current directory.
An existing .dbg file will be reused and a note printed to the transcript when the -debugdb switch is specified and your design has not changed since the database was created.
# compile testbench file vcom -93 -explicit -work work $srcpath_0/tb_xxx.vhd # run simulation vsim -L xxx -t 1ps tb_xxx