VHDL_LIB之DFF

1　　D-Flip-Flop with async reset or set

library IEEE;
use ieee.std_logic_1164.all;

entity FFD is
    generic
    (
        ResetVal    : std_logic := '0';        --! select async set / async reset
        ClockFall   : boolean := False         --! select clock edge
    );
    port
    (
        RST  :    in    std_logic;             　--! Async Reset
        C    :    in    std_logic;               --! Clock
        D    :    in    std_logic;               --! Input
        Q    :    out    std_logic               --! Output
    );
end FFD;

architecture beh of FFD is
    signal clock : std_logic;                    --! active clock

begin

gckr: if ClockFall = false generate
    clock <= C;
end generate;
gckf: if ClockFall = true generate
    clock <= not(C);
end generate;

pFF:    process(RST,clock)
        begin
            if(RST = '1') then
                Q <= ResetVal;
            else
                if(clock'Event and clock = '1') then
                    Q    <=    D;
                end if;
            end if;
        end process pFF;
end beh;

  

2　　D-Flip-Flop with clock enable

-- Port declaration
CE    :    in    std_logic;           --! Clock enable

-- Clock event
    if(clock'Event and clock = '1') then
        if (CE = '1') then　　Q <= D; 
        end if;        
    end if;