Program counter
The program is stored in memory with the first instruction at binary address 0000, the second instruction at address 0001, the third at address 0010 and so on. The program counter, which is part of the control unit, counts from 0000 to 1111. Its job is to send to the memory the address of next instruction.
The program counter is reset to 0000 before computer run. When the computer run begins, the program counter sends address 0000 to the memory. The program counter is then incremented to get 0001. After the first instruction is fetched and executed, the program counter sends address 0001 to the memory. Again the program counter is incremented. After the second isntruction is fetched and executed, the program counter sends address 0010 to the memory. In this way, the program counter is keeping track of the next instruction to be fetched and executed.
The program counter is like someone pointing at a list of instruction, saying do this first, do this second, etc. This is why the program counter is sometimes called a pointer; it points to an address in memory where something important is being stored.
1 library IEEE; 2 use ieee.std_logic_1164.all; 3 use ieee.std_logic_unsigned.all; 4 5 entity PC is 6 port 7 ( 8 EP : in std_logic; --! Active high output enable from PC, or tri-state 9 CLR : in std_logic; --! Active high asynchronous clear 10 CLK : in std_logic; --! Falling edge clock 11 CP : in std_logic; --! Active high enable PC to count 12 Q : out std_logic_vector(3 downto 0) --! 4-bit PC output 13 ); 14 end PC ; 15 16 architecture beh of PC is 17 18 signal count : std_logic_vector(3 downto 0); 19 20 begin 21 22 process (CLR,EP,CP,CLK,count) 23 begin 24 if CLR = '1' then 25 Q <= "0000"; 26 count <= "0000"; 27 elsif CP = '1' then 28 if (CLK'event and CLK = '0') then 29 if count < "1111" then 30 count <= count + 1; 31 else 32 count <= "0000"; 33 end if; 34 end if; 35 end if; 36 37 if EP = '0' then 38 Q <= "ZZZZ"; 39 else 40 Q <= count; 41 end if; 42 43 end process; 44 45 end beh;
Question: why do not use the following code in process?
1 begin 2 if EP = '0' then 3 Q <= "ZZZZ"; 4 elsif CLR = '1' then 5 Q <= "0000"; 6 count <= "0000"; 7 elsif CP = '1' then 8 if(CLK'event and CLK = '0') then 9 if count < "1111" then 10 count <= count + 1; 11 else 12 count <= "0000"; 13 end if; 14 end if; 15 end if; 16 17 end process;
Answer: first code, line 40, Q <= count
Own code for ASIC: use package ieee.numeric_std
1 library IEEE; 2 use ieee.std_logic_1164.all; 3 use ieee.numeric_std.all; 4 5 entity PC is 6 port 7 ( 8 EP : in std_logic; --! Active high output enable from PC, or tri-state 9 CLR : in std_logic; --! Active high asynchronous clear 10 CLK : in std_logic; --! Falling edge clock 11 CP : in std_logic; --! Active high enable PC to count 12 Q : out std_logic_vector(3 downto 0) --! 4-bit PC output 13 ); 14 end PC ; 15 16 architecture beh of PC is 17 18 signal count : std_logic_vector(3 downto 0); 19 20 begin 21 22 process (CLR,EP,CP,CLK,count) 23 begin 24 if CLR = '1' then 25 -- Q <= "0000"; 26 count <= "0000"; 27 elsif CP = '1' then 28 if (CLK'event and CLK = '0') then 29 if count < "1111" then 30 count <= std_logic_vector(unsigned(count) + 1); 31 else 32 count <= "0000"; 33 end if; 34 end if; 35 end if; 36 37 if EP = '0' then 38 Q <= "ZZZZ"; -- not good, in ASIC use only std_logic signal state '0', '1' 39 else 40 Q <= count; 41 end if; 42 43 end process; 44 45 end beh;
Question: In ASIC design, why use only std_logic signal states '0', '1'(and 'Z' for FPGA)???