Digital System Design Guidelines
By: Tony Goodloe (tony.goodloe@adtran.com)
--------------------------------------------------------------------------------
Synchronous Design Practices
(from CMOS/TTL Digital Systems Design, James Buchanan)
Clocked elements are clocked only by THE system clock.
Only a single-phase, single-frequency clock should be used.
All clocked elements should be edge-triggered (as opposed to latches or master-slave devices).
Clocked devices with TTL input levels should be selected so that all devices clock on the low-to-high clock transition.
Asynchronous presets and resets on clocked elements should never be used for performing operational system logic functions because of their susceptibility to noise.
Unclocked feedback paths (such as cross-coupled gates) should not be used because they are susceptible to being upset by system noise.
Never use a counter carry or a decoder output as a clock (such outputs are expected to have spikes).
Do not route asynchronous signals to multiple points within a functional unit until they are buffered and synchronized to the internal clock.
Monostable multivibrators (one-shots) should not be used.
--------------------------------------------------------------------------------
Power Distribution
(from CMOS/TTL Digital Systems Design, James Buchanan)
Planes should be used to distribute power and ground on circuit boards and motherboards. Ground reference planes are always required. Power may be distributed with a ladder or grid configuration but never with point-to-point wiring.
A continuous ground plane with no avoidance areas in IC package or pin connector fields on circuit boards or motherboards is always required.
Decoupling capacitors must be located as close as possible to active circuitry (i.e., component packages). A good rule of thumb is one decoupling capacitor per high current driver or memory device and one for every two packs of random logic.
Power supplies should be located as close as possible to the powered circuitry, and twisted-pair lines or closely coupled bus bars (to minimize the area between conductors, and hence the inductance) should be used to connect the power source to the local power distribution systems. When power must be remotely located, bulk decoupling capacitors should be used at the power entry points.
Ground pins must be evenly distributed across all connector pin fields (including custom device packages) to prevent local ground upset due to transient currents. The number of connector ground pins required must be determined from a system error budget. A rule of thumb for the minimum number of grounds in a connector is as follows: a minimum of one ground pin per inch of connector length or one per eight output signal lines.
When using prototyping boards (such as wire wrap, stitch weld, etc.), the power and ground planes must be continuous through the package- and connector-pin fields and the ground and power connections to component package pins, and board connectors must be made directly to the planes (solder washers or clips must be used on universal boards). Connecting power or ground with pc traces or with discrete wires is not permissible because such connections cause excessive inductance.
--------------------------------------------------------------------------------
FIFOs
Do not use sockets.
Place a 0.1 uF decoupling capacitor near each Vcc pin.
Place a ~470 pF filter capacitor near each Vcc pin. Leadless is best. Roger's (CCI) capacitor is next best alternative.
Terminate the Read and Write strobes. Thevenin termination to Vcc and Gnd is acceptable. AC termination uses less power and so is recommended.
Drive Read and Write stobes from a buffer (74F244) rather than directly from a PLD.
--------------------------------------------------------------------------------
Termination
Termination is required when signal trace length exceeds twice the signal rise time.
Match the value of the termination network to the characteristic impedance of the board. See Cypress or Motorola app notes mentioned at the end of this document (or many others) for characteristic impedanc of many PCB geometries. See "A Handbook of Blackmagic" mentioned at the end for more detailed formulae.
--------------------------------------------------------------------------------
PCB
Avoid stubs in nets with level-sensitive loads.
Structure the stack as follows to minimize layer-to-layer cross-talk:
Sig1
Power
Sig2
Space
Sig3
Ground
Sig4
Copper foil is referred to in ounces. For example, 1-oz foil weighs 1 oz per square foot and is about 0.0014 inch thick. Common foils are:
0.5 oz 0.00072 inch
1 oz 0.0014 inch
2 oz 0.0028 inch
Use polarity markers where appropriate - polarized caps, diodes, etc.
Route a net in a daisy-chain fashion rather than in a fanned-out fashion.
[The following is from "Murietta Circuits Design Layout Standards"]
Thru-Hole Grid .020
SMT Grid .010 and .025
Pin 1 on Components .055 square
Component Pads .055 (min of .020 larger than hole)
Component Holes .033
Anti-Pads (Plane Clearance) .085 (min of .050 larger than hole)
Soldermask Pads .065 (.010 larger for wet mask, .005 larger for dry or L.P.I)
Thru-Hole Via Pads .055
Thru-Hole Via Holes .033
SMT Via Pads .028 (.042 preferred)
SMT Via Holes .012 (.022 preferred)
Board Edge Pull Back on Planes .050
Board Edge Pull Back on S. Mask .025 (keep circuitry .050 from edge of board)
Signal Trace .008
Power and Ground Traces .050
Line to Line Spacing .008 (.013 on loose boards)
SMT Line to Pad Spacing .007
Thru-Hole Line to Pad Spacing .008
Pad to Pad Spacing .025 (Pad to via nad pad to pad spacing should be sufficient to insure soldermask coating between pads. Soldermask are bigger, so allow enough room between pads for a minimum of .015 coverage).
Pad to Via Centers .080
Test Height .075
Text Line Width .012
Annular Rings .020
Include the following on all artwork [from Murietta]
1. "Comp" and "Solder" in etch on their respective layers.
2. Add part number in etch on solder side.
3. Add "C 1993" and "Made in USA" in silkscreen legend.
4. Add serial number block in silkscreen legend.
5. Add company name or logo in silkscreen legend.
6. Add assembly number on silkscreen legend.
7. Somewhere outside the board geometry add the following information to
each sheet of artwork:
ABC Systems Corp.
Disk Interface board P/N 5678-22 REV. A
Comp. side Layer 1
Manufacturing Cost-cutting Tips [from Murietta]
A. Number of layers:
Limit the number of layers as much as possible. If higher
quantities are anticipated, spend the extra time and money in
engineering to insure it. Layout is a one-time expense,
manufacturing is not!
B. Number of holes sizes:
Limit the number of hole sizes. Each additional size adds to the
cost. Layout designers have considerable fexibility since hole
sizes can be .007-.015 larger than component lead sizes.
C. Small Hole size:
Try not to use hole sizes smaller than .028. They limit stack
drilling and drilling one board at a time greatly increases
machine time. Drills also break more often and plating becomes
more difficult. Holes .021 and smaller must be stack drilled 1
deep. Holes .022-.027 can be stack drilled 2 deep. Holes .028
and larger can be stack drilled 3 deep.
D. Annular Ring:
Try to provide pads that are .020 larger than hole size. Planned
annular ring of .010 is a good design criteria. Allowances must
be made for etching, lamination, drill position, front to back
registration, and film instability. Smaller annular ring is
certainly possible, but at the expense of lower yields and
increased manufacturing difficulty which results in higher cost.
E. Hole Tolerance:
If possible, do not specify hole tolerances any smaller than
.003. Boards are usaually pre-drilled .003-.004 larger than the
finished hole size to allow for copper plating inside the hole.
Drilling and copper plating are critical steps in manufacturing
circuit boards. tight tolerances just increase problems and
lower yields. A lot of material and labor go into a multilayer
board before it is drilled and plated. if it si out of
tolerenace, it is all scrap.
F. Copper Weight:
Do not specify 2 oz. copper unless you are sure you need it. 2
oz. material costs about 40% more than 1 oz.
G. Keep vias and component pads a minimum of .050 away from connector
gold-plated fingers. This will simplify the tape process and prevent
exposed bare copper after hot air solder leveling.
H. Internal cut-outs:
Avoid these if at all possible. These are very large holes and
require special routing. Also, make the board as small as
possible.
--------------------------------------------------------------------------------
PCB Design Flow
Run ERC on the schematics. Initial ALL errors and warnings, indicating that they are understood and acceptable.
Verify "n" nets from the schematics against the netlist and "n" different nets from the netlist against the schematics. (Pick "n" based on your comfort level.)
Verify each initialled error in the netlist.
Run DRC on the unrouted PCB (to catch pre-routed errors)
Route any critical nets (clocks, data strobes, etc.) manually.
Run DRC on the hand-routed PCB.
Autoroute the PCB.
If an autorouter is used, verify that the routes are "good enough." Don't be afraid the fix routes that look bad. Humans can do better than algorithms!
Run DRC on the auto-routed board.
Verify power and ground connections for each component on the routed PCB.
Verify "n" nets from the schematics against the routed PCB. Verify "n" nets from the routed PCB against the schematics.
Check each label (Connector ID, etc) on the board for correctness.
File a paper copy of each of the following: o Schematics o BOM o Initialed Electrical Rules Check report (schematic) o Netlist o Design Rule Check (PCB)
--------------------------------------------------------------------------------
Hardware Designer's Library
"Printed Circuits Design", Gerald Ginsberg,
McGraw Hill, ISBN 0-07-023309-8
A pretty good discussion of many aspects of PCB
design and manufacture
"Computation Structures", Stephen Ward and Robert H. Halstead Jr.,
MIT Press, ISBN 0-07-068147-3 (McGraw Hill), 0-262-23139-5 (MIT)
Introductory digital design/computer architecture
"CMOS/TTL Digital Systems Design", James Buchanan,
McGraw-Hill Publishing Company,
ISBN 0-07-008711-3, 1990
More advanced, real-world system design text
"The Art of Electronics", second edition, Horowitz and Hill,
Cambridge University Press, ISBN 0-521-37095-7, 1989
Introductory electronics
"High-Speed Digital Design - A Handbook of Black Magic", Howard
W. Johnson and Martin Graham, Prentice Hall,
ISBN 0-13-395724-1, 1993
Lots of physical effects, how to measure, reduce,
and calculate
--------------------------------------------------------------------------------
Stuff to Keep in Mind
Make sure you have the tools to do a job or a strong commitment
from a person with $ to buy the tools. Examples:
Fast enough scope (look at technology rise time)
Fast enough logic analyzer
Development software tools (PCB, schematic)
Analysis software tools (SPICE)
--------------------------------------------------------------------------------
Application Notes
"Applications Handbook", Cypress Semiconductor, 1989
"MECL System Design Handbook", Motorola Semiconductor, 1988
Not just for ECL designers!
--------------------------------------------------------------------------------
Books I've had recommended but haven't read
"Digital Printed Circuit Design and Drafting", Daryl Lindsey
available through Fine Line Printing, 800/560-8400.
--------------------------------------------------------------------------------
Hardware Designer's Library of Books about Software
"Operating Systems, Design and Implementation", Tannenbaum
"The Art of Computer Programming", Knuth
"The C Programming Language, Second Edition", Kernigan and Ritchie
"The Standard C Library", Plauger
--------------------------------------------------------------------------------
References
CMOS/TTL Digital Systems Design, James Buchanan
Applications Handbook, Cypress Semiconductor
Murrietta Circuits Design Layout Standards
Murrietta Circuits
Anaheim CA