1.This approach allows completely transparent mixed language, mixed-level, and mixed cycle-event simulations. It also lays the foundation for mixed signal simulations.
2.External Interface: (1) VHDL: VHPI,OMI (2) Verilog: PLI, VPI, OMI
3. After elaboration, Single executable code stream, Affirma NC Simulator;
4.Code Coverage ???
5. Verilog supported: (1) OVI 2.0; (2) IEEE 1364; (3) Verilog-XL implementation;
6. NC-Verilog use: Library.Cell:View cds.lib: This file contains statements that define your libraries and that map logical library names to physical directory paths. hdl.var: 决定哪个库为工作库.
7. You can write a setup.loc file to change the directories to search or to change the order of precedence to use when searching for the cds.lib and hdl.var files.
8.单步： ncverilog (分析器：ncvlog; ：ncelab,用来建立模型；启动ncsim仿真器仿真这个模型） 多步： 分别启动 ncvlog, ncelab, and ncsim
=> 单元绑定机制（cell binding mechanism ）是这两种方式的主要区别。
9.ncpack:change the properties of a database to make it read-only or add-only. inca.architecture.lib_version.pak inca.sun4v.091.pak ncls utility: list the objects contained in the library system,
10. Library files protect: (1) file locking mechanism: ncpack -unlock, to unlock a file (2) signal handling mechanism ensures that any unexpected event,
11. $>cdsdoc 启动cadence 文档窗口，是文档是html格式的 $> (tool_name) -help $> nchelp [options] tool_name message_code ******* ncsim> help [help_options] [command | all [command_options]]
11. nclaunch 图形界面的NC
SimVision Waveform. Viewer, 12. Many of these options have a corresponding plus option that you can use on the ncverilog command. ncvlog -ieee1364 => ncverilog +ncieee1364
When you run ncverilog, the parser is invoked with the -update option by default.
13. ncverilog: (1) +debug. 打开设计中所有对象的读权限 等同于ncelab -access +r (2) +access+. 使用该选项可以选择不同的权限 e.x.: +ncaccess+r, +ncaccess+r+w (3) +afile+access_file: 指定一个ACCESS文件
Three access: Enabling Read, Write, or Connectivity Access to Simulation Objects.
14. ncsim -licqueue: license队列
The NC-Verilog simulator command language is based on Tcl. TCL input file: +ncinput+filename or +tcl+filename;
15. ncverilog.args in the snap.nc directory: command-line options of ncverilog
cds.lib and hdl.var file in the INCA_libs directory.
All tools share a common log file named ncverilog.log.
Design units in files specified directly on the command line are compiled into the work library, and design units specified in -y libraries or -v library files are compiled into libraries that have the same names.
Writes the SNAPSHOT variable to the hdl.var file in the snap.nc directory to store the name of the snapshot used in this run.
---The SNAPSHOT variable in the hdl.var file is used to determine what snapshot was created the last time this directory was used.
16. The next time you invoke ncverilog, it compares the current set of command-line options to the options stored in the ncverilog.args file. All of the plus options and dash options must be the same and in the same order for the options to be evaluated as equal.
17. $> ncverilog +ncuid+ncuid_name 能用相同的中间对象和相同的存储空间去运行不同的仿真. 每个仿真必需提供一个唯一的ID.
18. ncverilog -h +all +cdslib+path +checkargs: Display a list of the arguments used on the command line. +compile: 仅仅用ncvlog编译,并不运行ncelab 和ncsim. +debug: 对设计中的所有对象都有读权限,等同于 +access+r. +elaborate: 运行 ncvlog和 ncelab +expand: Expand all vectors. +hdlvar+path -h +import: Prepare this Verilog design for import to VHDL. +mixedlang:Search the library structure for a VHDL binding for instances that correspond to VHDL import. +name+name: Use the specified name for the snapshot and for the INCA_libs/snap.nc directory. +ncelabargs+string:Pass the specified ncelab command options to the elaborator before invoking it. +ncelabexe+path_to_ncelab +ncerror+warning_code:Increase the severity level of the specified warning message from warning to error. +ncfatal+{warning_code | error_code}: Increase the severity level of the specified warning message or error message from warning or error to fatal. +nclibdirname+directory_name: to change INCA_libs +ncls_all:List all of the objects in all libraries. +ncls_dependents:Show the dependents for each object. +ncls_snapshots: List all snapshot (SSS) objects. +ncls_source:Show the source file dependents of each object. +ncsimargs+string +ncsimexe+path_to_ncsim +ncuid+ncuid_name +ncvlogargs+string +noautosdf:Do not perform. automatic SDF annotation. +noupdate: prevents the writing of intermediate objects for design units that are up-to-date. +ppe:Invoke the Post Processing Environment (PPE). -R: Invoke the simulator (ncsim) to simulate the snapshot in the INCA_libs/worklib directory. -r snapshot: Load the specified snapshot. +sdf_orig_dir:Put the compiled SDF file in same location as the original SDF file. +work+library_name: 使用用户指定的库作为工作库
-c Compile and elaborate only. //same to Verilog-XL
20. +tcl+filename,+ncinput+filename: NC-Verilog 仿真命令语言是基于TCL的,该选项加载tcl命令
21.The compiled SDF file:dcache.sdf.test1.X). Snapshots are always named lib.cell:ncuid_name
22. $test$plusargs % ncverilog -R +userarg % ncverilog -R +some_other_userarg
23. // To understand the concept of Snapshot % ncverilog source.v +ncuid+test1 % ncverilog source.v +ncuid+test2 Two snapshots are generated in the INCA_libs/worklib directory: worklib.top:test1 and worklib.top:test2.
you generate two snapshots using the following command lines: % ncverilog source.v +elaborate % ncverilog source.v +elaborate +access+r +nclibdirname+MYINCA_libs +name+debug
=> To simulate this snapshot: % ncverilog -R +nclibdirname+MYINCA_libs +name+debug [+simulator_options]
24.Using -r to Simulate a Saved Snapshot: % ncverilog -f verilog.vc +elaborate % ncverilog -R -s ncsim> run 1000 ncsim> save save1 ncsim> exit
//To simulate the saved snapshot, specify the snapshot name with the -r option, % ncverilog -r worklib.save1:v // or: ncverilog -r save1
=> Simulation Environment: If you want to restore the full Tcl debug environment when you restart with a saved snapshot, make sure that you save the environment with the save -environment filename command. This command creates a Tcl script. that captures the current breakpoints, databases, probes, aliases, and predefined Tcl variable values. You can then use the +ncinput+ option when you invoke ncverilog to execute the script, or you can invoke ncverilog in interactive mode with the -s option and then use the Tcl source command to source the script.
ncsim> save -environment ckpt1.tcl ncverilog -s -r worklib.top:ckpt1 +ncinput+ckpt1.tcl
Note: If you set a breakpoint that triggers, for example, every 10 ns (that is, at time 10, 20, 30, and so on) and restart with a snapshot saved at time 15, the breakpoint triggers at 20, 30, and so on, not at time 25, 35, and so on.
25. -R: The -R option lets you simulate the same snapshot multiple times using different simulator command-line options.
-r: You can use the -r option to load a snapshot.
26. SDF versions 1.0, 2.0, 2.1, and 3.0. For versions 2.0 and above, use the SDFVERSION statement in the header of the SDF file to specify the version.
SDF annotation is performed during elaboration. The elaborator recognizes $sdf_annotate system tasks in the design source files,
to override the default automatic SDF annotation mechanism and force annotation by using the +sdf_cmd_file+filename option
SDF: NC-Verilog 仿真器只能读取编译以后的SDF文件 (1) 文本SDF, cpu.sdf, (2) 编译后的文件: cpu.sdf.X.
ncsdfc 工具能自动地编译SDF文件
Using $test$plusargs to Selectively Perform. Annotations: if ($test$plusargs( preroute )) $sdf_annotate( preroute.sdf , m1); else if ($test$plusargs( postroute )) $sdf_annotate( postroute.sdf , m1);
The ncsdfc utility always compiles the SDF file with a precision of 1 fs. The elaborator annotates each module using the precision of the module or the precision set by using the ncelab -sdf_precision command_line option.
30.关闭 SDF 反标: (1) 在ncverilog 命令行中使用 +noautosdf 选项 (2) 在verilog源文件中,注释掉$sdf_annotate 系统任务
31. +sdf_cmd_file+filename
32.
You can use the -ieee1364 command-line option when you compile the design with ncvlog and elaborate the design with ncelab to check your code for compatibility with the IEEE standard.
33. IEEE 1364 - 1995 Verilog: array of instances, bufif0 ar[3:0] (out, in, en); // array of tri-state buffers However, an array of instances must have a continuous range.
34. 建立自己的环境,需要设置: cds.lib hdl.var setup.loc
35. Verilog: module, macromodule, or UDP VHDL: entity, architecture, package, package body, or configuration
36. internal intermediate objects: library database file (.pak file)
37. cds.lib: DEFINE worklib ../worklib DEFINE lib_std /usr1/libs/std_lib
You can have more than one cds.lib file. Use the INCLUDE or SOFTINCLUDE statements to include a cds.lib file within a cds.lib If you are doing a pure VHDL or a mixed-language simulation, you must use the INCLUDE or SOFTINCLUDE statement in the cds.lib (System provide one)
SOFTINCLUDE is the same as the INCLUDE statement, except that no error messages are printed if the file does not exist.
38. Binding One Library to Multiple Directories: DEFINE iclib ./ic_lib ASSIGN iclib TMP ./ic_tmp_lib ... UNASSIGN iclib TMP
38. -- can be used to check the content of the cds.lib % nchelp -cdslib
39. hdl.lib DEFINE WORK worklib DEFINE VERILOG_SUFFIX (.v, .vg, .vb) NCVLOGOPTS -messages -errormax 10 -update
40. hdl.var % nchelp -hdlvar
41. view & snapshot (1) The file mychip.v gets compiled into the default module view:worklib.mychip:module. It is created after compile, (ncvlog) (2) The elaborator generates a simulation snapshot for the design. Intermediate objects created during the elaboration phase are stored in the .pak file. The snapshot is also a Lib.Cell:View.
source =>(compile)=> module =>(elaborate) => snapshot => simulation, So the snapshot is the object of simulator