search_word

一个小程序，用asc码输出自己的名字。要求是，a~z两路输入，输出了一个完整的拼音之后还需要输出一个空格。—— 信息硬件过滤的雏形。

module search_word  (
                                                    clock ,
                                                    reset ,
                                                    d0,
                                                    d1,
                                                    word
                                                );
    //---------------------------------------------------------
    input                        clock ,reset;
    input              [6:0]   d0 ;   //A=65     M= 77
    input             [6:0]   d1 ;  //N = 78    Z = 90
    //----------------------------------------------------------
    output     reg [6:0]   word ; 
    
    // pengxiaoen   
    `define   P  7'd80   // D1
    `define   E  7'd69   //D0
    `define   N  7'd78  //D0 
    `define   G  7'd71  //D0
    `define   X  7'd88  //D1
    `define   I   7'd73  //D0
    `define   A  7'd65 //D0
    `define   O  7'd79  //D1
    `define   null   7'd32  //en
    
    `define  S0  4'd0
    `define  S1  4'd1
    `define  S2  4'd2
    `define  S3  4'd3
    `define  S4  4'd4
    `define  S5  4'd5
    `define  S6  4'd6
    `define  S7  4'd7
    `define  S8  4'd8
    `define  S9  4'd9
    `define  S10  4'd10

    reg  [3:0] current_state ; 
    reg [3:0]  next_state ;
    reg  data_sel ;   // 路由选通信号    1：  输出是d1    0 ： 输出是d0 
    reg   enable ;    // 输出使能信号   1 ： 输出空格    0：输出字母
    reg  [6:0]  data_reg ;  //数据缓存，缓存所选数据
    
    always @ (posedge clock or negedge reset )
            if (!reset )  current_state <= 4'd0 ; 
            else            current_state <= next_state ; 
    
    //always @ (*) 
    always @ (posedge clock  or negedge reset )
        begin 
                if(!reset)
                                next_state   <= 4'd0 ; 
                else  
                        begin 
                                case  (next_state)
                                        `S0   :   begin
                                                                if (data_reg == `P) 
                                                                                next_state  <= `S1; 
                                                               else     next_state  <= `S0 ;      // 等待P 的到来
                                                        end 
                                        `S1   :   begin
                                                                if (data_reg == `E) 
                                                                                next_state  <= next_state + 4'd1; 
                                                               else     next_state  <= `S1 ;      // 等待E 的到来
                                                        end 
                                        `S2   :   begin
                                                                if (data_reg == `N) 
                                                                              next_state  <= `S3; 
                                                               else    next_state  <= `S2 ;      // 等待N 的到来    
                                                        end 
                                        `S3   :   begin
                                                                if (data_reg == `G) 
                                                                                next_state  <= `S4; 
                                                               else     next_state  <= `S3 ;      // 等待G 的到来
                                                        end 
                                        `S4   :   begin 
                                                                if (data_reg == `X) 
                                                                                next_state  <= `S5; 
                                                               else        next_state  <= `S4;      // 等待X 的到来
                                                        end 
                                        `S5   :   begin
                                                                if (data_reg == `I) 
                                                                                next_state  <= `S6; 
                                                               else       next_state  <= `S5;      // 等待I 的到来
                                                        end 
                                        `S6   :   begin
                                                                if (data_reg == `A) 
                                                                                next_state  <= `S7; 
                                                               else     next_state  <= `S6 ;      // 等待A 的到来
                                                        end 
                                        `S7   :   begin
                                                                if (data_reg == `O) 
                                                                                next_state  <= `S8; 
                                                               else     next_state  <= `S7 ;      // 等待O 的到来
                                                        end 
                                        `S8  :   begin
                                                                if (data_reg == `E) 
                                                                                next_state  <= `S9; 
                                                               else     next_state  <= `S8 ;      // 等待E的到来
                                                        end 
                                        `S9  :   begin
                                                                if (data_reg == `N) 
                                                                                next_state  <= `S10; 
                                                               else     next_state  <= `S9 ;      // 等待N的到来
                                                      end 
                                        `S10  :  begin 
                                                                 next_state = `S0 ; 
                                                    end 
                                        default :  next_state <= `S0 ; 
                                endcase 
                        end 
        end 
        
        
        
        
            always @ (posedge clock  or negedge reset )
        begin 
                if(!reset)
                        begin 
                                data_sel      <= 1'd0 ;
                                enable         <= 1'd0 ; 
                        end
                else  
                        begin 
                                case  (current_state)
                                        `S0   :   begin
                                                                 enable       <=  1'd1; //0: 输出字母      1  ： 输出空格
                                                                 data_sel     <=  1'd1 ; // P属于通道1 
                                                        end 
                                        `S1   :   begin
                                                                 enable       <=  1'd0 ; 
                                                                 data_sel     <=  1'd0;  //E 属于通道 0
                                                        end 
                                        `S2   :   begin
                                                                 enable       <=  1'd0 ; 
                                                                 data_sel     <=  1'd1 ; // N 属于通道1
                                                        end 
                                        `S3   :   begin
                                                             enable       <=  1'd0;  // 输出字母
                                                                    data_sel     <= 1'd0 ;  // G 属于通道0 
                                                                    
                                                        end 
                                        `S4   :   begin 
                                                                    enable       <=  1'd1 ;   //输出空格
                                                                    data_sel     <=  1'd1 ; //X 属于通道1 
                                                        end 
                                        `S5   :   begin
                                                                 enable       <=  1'd0 ; 
                                                                 data_sel     <=  1'd0 ; // I 属于通道0 
                                                        end 
                                        `S6   :   begin
                                                                 enable       <=  1'd0 ; 
                                                                 data_sel    <=  1'd0 ;  // A 为通道0 
                                                        end 
                                        `S7   :   begin
                                                           enable       <=  1'd0 ; 
                                                                 data_sel    <=  1'd1 ;   // O 属于通道1 
                                                        end 
                                        `S8  :   begin
                                                                 enable       <=  1'd1 ;  //输出空格 
                                                                 data_sel    <=  1'd0 ;  // E 属于通道0 
                                                        end 
                                        `S9  :   begin
                                                                enable        <=  1'd0 ;   // 
                                                                data_sel     <=  1'd1 ;   // N 属于通道 1 
                                                      end 
                                        `S10  :  begin 
                                                          enable         <=1'd0 ;   // 输出
                                                                data_sel      <= 1'd1;  // P 属于通道1 
                                                    end 
                                endcase 
                        end 
        end
    
 always  @ (posedge clock  or negedge reset )    
//  always  @ (*)
        begin 
                if (!reset )   data_reg  <=  7'd0 ; 
                else 
                        begin 
                                if (data_sel)  data_reg  <= d1 ; 
                                else               data_reg  <= d0 ; 
                        end 
        end 
        
    always @ (posedge clock  or negedge reset )
        begin 
                if(!reset)  word   <=   7'd0 ; 
                else  if(!enable)
                        begin 
                                case  (current_state)
                                      `S0   :   word   <= `null;
                                        `S1   :   word   <= `P;
                                        `S2   :    word   <= `E;  
                                        `S3   :   word   <= `N;
                                        `S4   :   word   <= `G;
                                        `S5   :   word   <= `X;
                                        `S6   :   word   <= `I;
                                        `S7   :   word   <= `A;
                                        `S8   :   word   <= `O;
                                        `S9  :    word   <= `E;
                                        `S10  :    word   <= `N;
                                        default  :  word  <= 7'd0 ; 
                                endcase 
                        end 
                else  word  <= 7'b010_0000;
        end 

endmodule 

附上testbench ，亲测可用

`timescale  1ns/1ps 

module search_word_tb  ;
reg         clock ,reset ;
reg [6:0]  d0 ,d1 ; 
wire [6:0]word ; 

integer i ,j ; 

always #10 clock = ~clock ; 

initial 
        begin 
                clock = 0 ; reset = 0  ; 
                #50 reset = 1  ; 
                
        end 

initial 
        begin 
                 d0 = 7'd0 ; 
                 # 50  ; 
                 repeat (1000)
                        begin 
                                for (i = 0;i <=12 ; i=i+1)  
                                  begin 
                                         # 20   d0 = 7'd65 + i ; 
                                end 
                        end 
        end 
        
initial 
        begin 
                 d1 = 7'd0 ; 
                 # 50  ; 
                  repeat (1000)
                  begin 
                        for (j = 0;j  <=12 ; j=j+1)  
                                begin 
                                        # 20 d1 = 7'd78 + j; 
                                end 
                    end 
        end 

 search_word  myu0 (
                                                    .clock (clock ),
                                                    .reset (reset ),
                                                    .d0(d0),
                                                    .d1(d1),
                                                    .word (word )
                                                );



endmodule