Timer triggered DMA transfer

Hello,

I'm working with a STM32F407 controller board.

 

Right now, I want to trigger a DMA transfer with one of the internal timers (TIM1).

 

The DMA transfer should read one gpio port and put it into the memory.

 

The timer is configured in PWM mode and should trigger the DMA transfer

 

on "update" (counter value is reset to 0) and on "compare" (output pin is toggled). 

 

I haven't tested this configuration right now, but as far as I read in the manual

 

both events (update and compare) should be able to start the DMA transfer.

My question is, what's the delay between requesting the DMA transfer

 

with the timer and reading the data from the port?

 

This is important for me, because the PWM signal of the timer clocks an external ADC

 

and the DMA transfer should copy the external ADC data into the internal memory.

 

The ADC data is available 6ns after the rising edge of the clock.

 

So, the DMA transfer must not start earlier than 6ns after getting triggered (6ns is one cpu clock).

Is there a good application note of how to setup a timer triggered DMA transfer?

Thanks a lot,
Andreas

 

It's probably rather indeterminate, the internal clock edge is going to occur ahead of anything exiting the package.

 

The delay between the clock, and DMA transfer, is going to depend on things

 

like bus contention, channel contention, pending writes, prefetches, slow accessed to peripheral buses, etc.

For tighter edge to transfer timings look at the FSMC or DCMI interfaces.

Input signals are also resynchronized, so different clocking speeds

 

will result in beating/modulation as they cross domains.

 

 

Thanks for your reply. DMA transfers seem to depend on a lot of conditions. 

It is intended to clock the CCD sensor and the ADCs with about 20 MHz.

 

This would result in at least to bytes from the ADCs every clock cycle (40MByte/s or 320MBit/s).

Would that transfer rate be possible with the DMA controller?

I will have a look at  FSMC and DCMI interfaces.

BTW, is it possible to give a upper bound for the delay between DMA request and transfer?

 

In my application the DMA transfer (copy one word to internal memory) must be completed within 25ns.

 

My gut says the potential latency is a lot higher than 25ns, a flash line access is of the order of 35 ns.

 

An APB access, in the order of 4 APB cycles, at whatever clock rate that's set too.

 

It would take a lot of time/effort to quantify.

You'd need a FIFO to manage latency and throughput.

 

You're looking for a more "Direct" memory access.