1.前言
本文主要对freescale芯片 MK64F12的启动汇编文件进行注释解析。
2.文件注释
1 /* ---------------------------------------------------------------------------------------*/ 2 /* @file: startup_MK64F12.s */ 3 /* @purpose: CMSIS Cortex-M4 Core Device Startup File */ 4 /* MK64F12 */ 5 /* @version: 2.7 */ 6 /* @date: 2014-10-14 */ 7 /* @build: b150126 */ 8 /* ---------------------------------------------------------------------------------------*/ 9 /* */ 10 /* Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. */ 11 /* All rights reserved. */ 12 /* */ 13 /* Redistribution and use in source and binary forms, with or without modification, */ 14 /* are permitted provided that the following conditions are met: */ 15 /* */ 16 /* o Redistributions of source code must retain the above copyright notice, this list */ 17 /* of conditions and the following disclaimer. */ 18 /* */ 19 /* o Redistributions in binary form must reproduce the above copyright notice, this */ 20 /* list of conditions and the following disclaimer in the documentation and/or */ 21 /* other materials provided with the distribution. */ 22 /* */ 23 /* o Neither the name of Freescale Semiconductor, Inc. nor the names of its */ 24 /* contributors may be used to endorse or promote products derived from this */ 25 /* software without specific prior written permission. */ 26 /* */ 27 /* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ 28 /* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ 29 /* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ 30 /* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ 31 /* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ 32 /* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ 33 /* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ 34 /* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ 35 /* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ 36 /* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 37 /*****************************************************************************/ 38 /* Version: GCC for ARM Embedded Processors */ 39 /*****************************************************************************/ 40 .syntax unified /* 指示arm和thumb指令将使用统一的格式 */ 41 .arch armv7-m /* 指示体系结构为armv7-m */ 42 43 .section .isr_vector, "a" /* 定义段名为isr_vector的段，ELF格式允许的段标志： a：可分配 w：可写段 x：执行段 ,每一个段以段名为开始，以下一个段名或者文件结尾为结束*/
44 .align 2 /*align对齐到2^2*/ 45 .globl __isr_vector /*定义全局符号*/ 46 __isr_vector: 47 .long __StackTop /* Top of Stack */ /* 定义4字节数据 */ 48 .long Reset_Handler /* Reset Handler */ 49 .long NMI_Handler /* NMI Handler*/ 50 .long HardFault_Handler /* Hard Fault Handler*/ 51 .long MemManage_Handler /* MPU Fault Handler*/ 52 .long BusFault_Handler /* Bus Fault Handler*/ 53 .long UsageFault_Handler /* Usage Fault Handler*/ 54 .long 0 /* Reserved*/ 55 .long 0 /* Reserved*/ 56 .long 0 /* Reserved*/ 57 .long 0 /* Reserved*/ 58 .long SVC_Handler /* SVCall Handler*/ 59 .long DebugMon_Handler /* Debug Monitor Handler*/ 60 .long 0 /* Reserved*/ 61 .long PendSV_Handler /* PendSV Handler*/ 62 .long SysTick_Handler /* SysTick Handler*/ 63 64 /* External Interrupts*/ 65 .long DMA0_IRQHandler /* DMA Channel 0 Transfer Complete*/ 66 .long DMA1_IRQHandler /* DMA Channel 1 Transfer Complete*/ 67 .long DMA2_IRQHandler /* DMA Channel 2 Transfer Complete*/ 68 .long DMA3_IRQHandler /* DMA Channel 3 Transfer Complete*/ 69 .long DMA4_IRQHandler /* DMA Channel 4 Transfer Complete*/ 70 .long DMA5_IRQHandler /* DMA Channel 5 Transfer Complete*/ 71 .long DMA6_IRQHandler /* DMA Channel 6 Transfer Complete*/ 72 .long DMA7_IRQHandler /* DMA Channel 7 Transfer Complete*/ 73 .long DMA8_IRQHandler /* DMA Channel 8 Transfer Complete*/ 74 .long DMA9_IRQHandler /* DMA Channel 9 Transfer Complete*/ 75 .long DMA10_IRQHandler /* DMA Channel 10 Transfer Complete*/ 76 .long DMA11_IRQHandler /* DMA Channel 11 Transfer Complete*/ 77 .long DMA12_IRQHandler /* DMA Channel 12 Transfer Complete*/ 78 .long DMA13_IRQHandler /* DMA Channel 13 Transfer Complete*/ 79 .long DMA14_IRQHandler /* DMA Channel 14 Transfer Complete*/ 80 .long DMA15_IRQHandler /* DMA Channel 15 Transfer Complete*/ 81 .long DMA_Error_IRQHandler /* DMA Error Interrupt*/ 82 .long MCM_IRQHandler /* Normal Interrupt*/ 83 .long FTFE_IRQHandler /* FTFE Command complete interrupt*/ 84 .long Read_Collision_IRQHandler /* Read Collision Interrupt*/ 85 .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/ 86 .long LLW_IRQHandler /* Low Leakage Wakeup*/ 87 .long WDOG_EWM_IRQHandler /* WDOG Interrupt*/ 88 .long RNG_IRQHandler /* RNG Interrupt*/ 89 .long I2C0_IRQHandler /* I2C0 interrupt*/ 90 .long I2C1_IRQHandler /* I2C1 interrupt*/ 91 .long SPI0_IRQHandler /* SPI0 Interrupt*/ 92 .long SPI1_IRQHandler /* SPI1 Interrupt*/ 93 .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/ 94 .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/ 95 .long UART0_LON_IRQHandler /* UART0 LON interrupt*/ 96 .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/ 97 .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/ 98 .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/ 99 .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/ 100 .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/ 101 .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/ 102 .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/ 103 .long UART3_ERR_IRQHandler /* UART3 Error interrupt*/ 104 .long ADC0_IRQHandler /* ADC0 interrupt*/ 105 .long CMP0_IRQHandler /* CMP0 interrupt*/ 106 .long CMP1_IRQHandler /* CMP1 interrupt*/ 107 .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/ 108 .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/ 109 .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/ 110 .long CMT_IRQHandler /* CMT interrupt*/ 111 .long RTC_IRQHandler /* RTC interrupt*/ 112 .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/ 113 .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/ 114 .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/ 115 .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/ 116 .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/ 117 .long PDB0_IRQHandler /* PDB0 Interrupt*/ 118 .long USB0_IRQHandler /* USB0 interrupt*/ 119 .long USBDCD_IRQHandler /* USBDCD Interrupt*/ 120 .long Reserved71_IRQHandler /* Reserved interrupt 71*/ 121 .long DAC0_IRQHandler /* DAC0 interrupt*/ 122 .long MCG_IRQHandler /* MCG Interrupt*/ 123 .long LPTMR0_IRQHandler /* LPTimer interrupt*/ 124 .long PORTA_IRQHandler /* Port A interrupt*/ 125 .long PORTB_IRQHandler /* Port B interrupt*/ 126 .long PORTC_IRQHandler /* Port C interrupt*/ 127 .long PORTD_IRQHandler /* Port D interrupt*/ 128 .long PORTE_IRQHandler /* Port E interrupt*/ 129 .long SWI_IRQHandler /* Software interrupt*/ 130 .long SPI2_IRQHandler /* SPI2 Interrupt*/ 131 .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/ 132 .long UART4_ERR_IRQHandler /* UART4 Error interrupt*/ 133 .long UART5_RX_TX_IRQHandler /* UART5 Receive/Transmit interrupt*/ 134 .long UART5_ERR_IRQHandler /* UART5 Error interrupt*/ 135 .long CMP2_IRQHandler /* CMP2 interrupt*/ 136 .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/ 137 .long DAC1_IRQHandler /* DAC1 interrupt*/ 138 .long ADC1_IRQHandler /* ADC1 interrupt*/ 139 .long I2C2_IRQHandler /* I2C2 interrupt*/ 140 .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/ 141 .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/ 142 .long CAN0_Error_IRQHandler /* CAN0 error interrupt*/ 143 .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/ 144 .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/ 145 .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/ 146 .long SDHC_IRQHandler /* SDHC interrupt*/ 147 .long ENET_1588_Timer_IRQHandler /* Ethernet MAC IEEE 1588 Timer Interrupt*/ 148 .long ENET_Transmit_IRQHandler /* Ethernet MAC Transmit Interrupt*/ 149 .long ENET_Receive_IRQHandler /* Ethernet MAC Receive Interrupt*/ 150 .long ENET_Error_IRQHandler /* Ethernet MAC Error and miscelaneous Interrupt*/ 151 .long DefaultISR /* 102*/ 152 .long DefaultISR /* 103*/ 153 .long DefaultISR /* 104*/ 154 .long DefaultISR /* 105*/ 155 .long DefaultISR /* 106*/ 156 .long DefaultISR /* 107*/ 157 .long DefaultISR /* 108*/ 158 .long DefaultISR /* 109*/ 159 .long DefaultISR /* 110*/ 160 .long DefaultISR /* 111*/ 161 .long DefaultISR /* 112*/ 162 .long DefaultISR /* 113*/ 163 .long DefaultISR /* 114*/ 164 .long DefaultISR /* 115*/ 165 .long DefaultISR /* 116*/ 166 .long DefaultISR /* 117*/ 167 .long DefaultISR /* 118*/ 168 .long DefaultISR /* 119*/ 169 .long DefaultISR /* 120*/ 170 .long DefaultISR /* 121*/ 171 .long DefaultISR /* 122*/ 172 .long DefaultISR /* 123*/ 173 .long DefaultISR /* 124*/ 174 .long DefaultISR /* 125*/ 175 .long DefaultISR /* 126*/ 176 .long DefaultISR /* 127*/ 177 .long DefaultISR /* 128*/ 178 .long DefaultISR /* 129*/ 179 .long DefaultISR /* 130*/ 180 .long DefaultISR /* 131*/ 181 .long DefaultISR /* 132*/ 182 .long DefaultISR /* 133*/ 183 .long DefaultISR /* 134*/ 184 .long DefaultISR /* 135*/ 185 .long DefaultISR /* 136*/ 186 .long DefaultISR /* 137*/ 187 .long DefaultISR /* 138*/ 188 .long DefaultISR /* 139*/ 189 .long DefaultISR /* 140*/ 190 .long DefaultISR /* 141*/ 191 .long DefaultISR /* 142*/ 192 .long DefaultISR /* 143*/ 193 .long DefaultISR /* 144*/ 194 .long DefaultISR /* 145*/ 195 .long DefaultISR /* 146*/ 196 .long DefaultISR /* 147*/ 197 .long DefaultISR /* 148*/ 198 .long DefaultISR /* 149*/ 199 .long DefaultISR /* 150*/ 200 .long DefaultISR /* 151*/ 201 .long DefaultISR /* 152*/ 202 .long DefaultISR /* 153*/ 203 .long DefaultISR /* 154*/ 204 .long DefaultISR /* 155*/ 205 .long DefaultISR /* 156*/ 206 .long DefaultISR /* 157*/ 207 .long DefaultISR /* 158*/ 208 .long DefaultISR /* 159*/ 209 .long DefaultISR /* 160*/ 210 .long DefaultISR /* 161*/ 211 .long DefaultISR /* 162*/ 212 .long DefaultISR /* 163*/ 213 .long DefaultISR /* 164*/ 214 .long DefaultISR /* 165*/ 215 .long DefaultISR /* 166*/ 216 .long DefaultISR /* 167*/ 217 .long DefaultISR /* 168*/ 218 .long DefaultISR /* 169*/ 219 .long DefaultISR /* 170*/ 220 .long DefaultISR /* 171*/ 221 .long DefaultISR /* 172*/ 222 .long DefaultISR /* 173*/ 223 .long DefaultISR /* 174*/ 224 .long DefaultISR /* 175*/ 225 .long DefaultISR /* 176*/ 226 .long DefaultISR /* 177*/ 227 .long DefaultISR /* 178*/ 228 .long DefaultISR /* 179*/ 229 .long DefaultISR /* 180*/ 230 .long DefaultISR /* 181*/ 231 .long DefaultISR /* 182*/ 232 .long DefaultISR /* 183*/ 233 .long DefaultISR /* 184*/ 234 .long DefaultISR /* 185*/ 235 .long DefaultISR /* 186*/ 236 .long DefaultISR /* 187*/ 237 .long DefaultISR /* 188*/ 238 .long DefaultISR /* 189*/ 239 .long DefaultISR /* 190*/ 240 .long DefaultISR /* 191*/ 241 .long DefaultISR /* 192*/ 242 .long DefaultISR /* 193*/ 243 .long DefaultISR /* 194*/ 244 .long DefaultISR /* 195*/ 245 .long DefaultISR /* 196*/ 246 .long DefaultISR /* 197*/ 247 .long DefaultISR /* 198*/ 248 .long DefaultISR /* 199*/ 249 .long DefaultISR /* 200*/ 250 .long DefaultISR /* 201*/ 251 .long DefaultISR /* 202*/ 252 .long DefaultISR /* 203*/ 253 .long DefaultISR /* 204*/ 254 .long DefaultISR /* 205*/ 255 .long DefaultISR /* 206*/ 256 .long DefaultISR /* 207*/ 257 .long DefaultISR /* 208*/ 258 .long DefaultISR /* 209*/ 259 .long DefaultISR /* 210*/ 260 .long DefaultISR /* 211*/ 261 .long DefaultISR /* 212*/ 262 .long DefaultISR /* 213*/ 263 .long DefaultISR /* 214*/ 264 .long DefaultISR /* 215*/ 265 .long DefaultISR /* 216*/ 266 .long DefaultISR /* 217*/ 267 .long DefaultISR /* 218*/ 268 .long DefaultISR /* 219*/ 269 .long DefaultISR /* 220*/ 270 .long DefaultISR /* 221*/ 271 .long DefaultISR /* 222*/ 272 .long DefaultISR /* 223*/ 273 .long DefaultISR /* 224*/ 274 .long DefaultISR /* 225*/ 275 .long DefaultISR /* 226*/ 276 .long DefaultISR /* 227*/ 277 .long DefaultISR /* 228*/ 278 .long DefaultISR /* 229*/ 279 .long DefaultISR /* 230*/ 280 .long DefaultISR /* 231*/ 281 .long DefaultISR /* 232*/ 282 .long DefaultISR /* 233*/ 283 .long DefaultISR /* 234*/ 284 .long DefaultISR /* 235*/ 285 .long DefaultISR /* 236*/ 286 .long DefaultISR /* 237*/ 287 .long DefaultISR /* 238*/ 288 .long DefaultISR /* 239*/ 289 290 #ifdef BL_HAS_BOOTLOADER_CONFIG 291 292 //__bootloaderConfigurationArea ; 0x3c0 293 // .long 'kcfg' // [00:03] tag - Tag value used to validate the bootloader configuration data. Must be set to 'kcfg' 294 .long 0x6766636b 295 .long 0xFFFFFFFF // [04:07] crcStartAddress 296 .long 0xFFFFFFFF // [08:0b] crcByteCount 297 .long 0xFFFFFFFF // [0c:0f] crcExpectedValue 298 .byte 0xFF // [10:10] enabledPeripherals 299 .byte 0xFF // [11:11] i2cSlaveAddress 300 .short 5000 // [12:13] peripheralDetectionTimeoutMs - Timeout in milliseconds for peripheral detection before jumping to application code 301 .short 0xFFFF // [14:15] usbVid 302 .short 0xFFFF // [16:17] usbPid 303 .long 0xFFFFFFFF // [18:1b] usbStringsPointer 304 .byte 0xFF // [1c:1c] clockFlags - High Speed and other clock options 305 .byte 0xFF // [1d:1d] clockDivider - One's complement of clock divider, zero divider is divide by 1 306 .short 0xFFFF // [1e:1f] reserved 307 // Fill to align with flash configuration field. 308 .long 0xFFFFFFFF 309 .long 0xFFFFFFFF 310 .long 0xFFFFFFFF 311 .long 0xFFFFFFFF 312 .long 0xFFFFFFFF 313 .long 0xFFFFFFFF 314 .long 0xFFFFFFFF 315 .long 0xFFFFFFFF // Reserved for user TRIM value 316 #else 317 //Fill to align with flash configuration field. 318 .long 0xFFFFFFFF 319 .long 0xFFFFFFFF 320 .long 0xFFFFFFFF 321 .long 0xFFFFFFFF 322 .long 0xFFFFFFFF 323 .long 0xFFFFFFFF 324 .long 0xFFFFFFFF 325 .long 0xFFFFFFFF 326 .long 0xFFFFFFFF 327 .long 0xFFFFFFFF 328 .long 0xFFFFFFFF 329 .long 0xFFFFFFFF 330 .long 0xFFFFFFFF 331 .long 0xFFFFFFFF 332 .long 0xFFFFFFFF 333 .long 0xFFFFFFFF // Reserved for user TRIM value 334 #endif // BL_HAS_BOOTLOADER_CONFIG 335 .size __isr_vector, . - __isr_vector 336 337 /* Flash Configuration */ 338 .section .FlashConfig, "a" 339 .long 0xFFFFFFFF 340 .long 0xFFFFFFFF 341 .long 0xFFFFFFFF 342 .long 0xFFFFFFFE 343 344 .text 345 .thumb 346 347 /* Reset Handler */ 348 349 .thumb_func 350 .align 2 351 .globl Reset_Handler 352 .weak Reset_Handler 353 .type Reset_Handler, %function 354 Reset_Handler: 355 cpsid i /* Mask interrupts */ 356 #ifndef __NO_SYSTEM_INIT 357 bl SystemInit 358 #endif 359 bl init_data_bss 360 cpsie i /* Unmask interrupts */ 361 #ifndef __START 362 #define __START _start 363 #endif 364 #ifndef __ATOLLIC__ 365 bl __START 366 #else 367 bl __libc_init_array 368 bl main 369 #endif 370 .pool 371 .size Reset_Handler, . - Reset_Handler 372 373 .align 1 374 .thumb_func 375 .weak DefaultISR 376 .type DefaultISR, %function 377 DefaultISR: 378 b DefaultISR 379 .size DefaultISR, . - DefaultISR 380 381 /* Macro to define default handlers. Default handler 382 * will be weak symbol and just dead loops. They can be 383 * overwritten by other handlers */ 384 .macro def_irq_handler handler_name 385 .weak handler_name 386 .set handler_name, DefaultISR 387 .endm 388 389 /* Exception Handlers */ 390 def_irq_handler NMI_Handler 391 def_irq_handler HardFault_Handler 392 def_irq_handler MemManage_Handler 393 def_irq_handler BusFault_Handler 394 def_irq_handler UsageFault_Handler 395 def_irq_handler SVC_Handler 396 def_irq_handler DebugMon_Handler 397 def_irq_handler PendSV_Handler 398 def_irq_handler SysTick_Handler 399 def_irq_handler DMA0_IRQHandler 400 def_irq_handler DMA1_IRQHandler 401 def_irq_handler DMA2_IRQHandler 402 def_irq_handler DMA3_IRQHandler 403 def_irq_handler DMA4_IRQHandler 404 def_irq_handler DMA5_IRQHandler 405 def_irq_handler DMA6_IRQHandler 406 def_irq_handler DMA7_IRQHandler 407 def_irq_handler DMA8_IRQHandler 408 def_irq_handler DMA9_IRQHandler 409 def_irq_handler DMA10_IRQHandler 410 def_irq_handler DMA11_IRQHandler 411 def_irq_handler DMA12_IRQHandler 412 def_irq_handler DMA13_IRQHandler 413 def_irq_handler DMA14_IRQHandler 414 def_irq_handler DMA15_IRQHandler 415 def_irq_handler DMA_Error_IRQHandler 416 def_irq_handler MCM_IRQHandler 417 def_irq_handler FTFE_IRQHandler 418 def_irq_handler Read_Collision_IRQHandler 419 def_irq_handler LVD_LVW_IRQHandler 420 def_irq_handler LLW_IRQHandler 421 def_irq_handler WDOG_EWM_IRQHandler 422 def_irq_handler RNG_IRQHandler 423 def_irq_handler I2C0_IRQHandler 424 def_irq_handler I2C1_IRQHandler 425 def_irq_handler SPI0_IRQHandler 426 def_irq_handler SPI1_IRQHandler 427 def_irq_handler I2S0_Tx_IRQHandler 428 def_irq_handler I2S0_Rx_IRQHandler 429 def_irq_handler UART0_LON_IRQHandler 430 def_irq_handler UART0_RX_TX_IRQHandler 431 def_irq_handler UART0_ERR_IRQHandler 432 def_irq_handler UART1_RX_TX_IRQHandler 433 def_irq_handler UART1_ERR_IRQHandler 434 def_irq_handler UART2_RX_TX_IRQHandler 435 def_irq_handler UART2_ERR_IRQHandler 436 def_irq_handler UART3_RX_TX_IRQHandler 437 def_irq_handler UART3_ERR_IRQHandler 438 def_irq_handler ADC0_IRQHandler 439 def_irq_handler CMP0_IRQHandler 440 def_irq_handler CMP1_IRQHandler 441 def_irq_handler FTM0_IRQHandler 442 def_irq_handler FTM1_IRQHandler 443 def_irq_handler FTM2_IRQHandler 444 def_irq_handler CMT_IRQHandler 445 def_irq_handler RTC_IRQHandler 446 def_irq_handler RTC_Seconds_IRQHandler 447 def_irq_handler PIT0_IRQHandler 448 def_irq_handler PIT1_IRQHandler 449 def_irq_handler PIT2_IRQHandler 450 def_irq_handler PIT3_IRQHandler 451 def_irq_handler PDB0_IRQHandler 452 def_irq_handler USB0_IRQHandler 453 def_irq_handler USBDCD_IRQHandler 454 def_irq_handler Reserved71_IRQHandler 455 def_irq_handler DAC0_IRQHandler 456 def_irq_handler MCG_IRQHandler 457 def_irq_handler LPTMR0_IRQHandler 458 def_irq_handler PORTA_IRQHandler 459 def_irq_handler PORTB_IRQHandler 460 def_irq_handler PORTC_IRQHandler 461 def_irq_handler PORTD_IRQHandler 462 def_irq_handler PORTE_IRQHandler 463 def_irq_handler SWI_IRQHandler 464 def_irq_handler SPI2_IRQHandler 465 def_irq_handler UART4_RX_TX_IRQHandler 466 def_irq_handler UART4_ERR_IRQHandler 467 def_irq_handler UART5_RX_TX_IRQHandler 468 def_irq_handler UART5_ERR_IRQHandler 469 def_irq_handler CMP2_IRQHandler 470 def_irq_handler FTM3_IRQHandler 471 def_irq_handler DAC1_IRQHandler 472 def_irq_handler ADC1_IRQHandler 473 def_irq_handler I2C2_IRQHandler 474 def_irq_handler CAN0_ORed_Message_buffer_IRQHandler 475 def_irq_handler CAN0_Bus_Off_IRQHandler 476 def_irq_handler CAN0_Error_IRQHandler 477 def_irq_handler CAN0_Tx_Warning_IRQHandler 478 def_irq_handler CAN0_Rx_Warning_IRQHandler 479 def_irq_handler CAN0_Wake_Up_IRQHandler 480 def_irq_handler SDHC_IRQHandler 481 def_irq_handler ENET_1588_Timer_IRQHandler 482 def_irq_handler ENET_Transmit_IRQHandler 483 def_irq_handler ENET_Receive_IRQHandler 484 def_irq_handler ENET_Error_IRQHandler 485 486 .end