Every cell has multipletiming arcs. For example, a combinational logic cell, such as and, or, nand, nor, adder cell, has timing arcs from each input to each output of the cell. Sequential cells such as flip-flops have timing arcs from the clock to the outputs and timing constraints for the data pins with respect to the clock. Each timing arc has a timing sense, that is, how the output changes for different types of transitions on input. The timing arc ispositive unate if a rising transition on an input causes the output to rise (or not to change) and a falling transition on an input causes the output to fall (or not to change).
A
negative unate timing arc is one where a rising transition on an
input causes the output to have a falling transition (or not to change)
and a fall-ing transition on an input causes the output to have a rising
transition (or
not to change).For example, the timing arcs for nand and nor type cells are
negative unate.
In a non-unate timing arc, the output transition cannot be determined solely from the direction of change of an input but also depends upon the state of the other inputs. For example, the timing arcs in an xor cell (exclusive-or) are non-unate.
Unateness is important for timing as it specifies how the edges (transitions)
can propagate through a cell and how they appear at the output of the cell.
Each timing arc has a startpoint and an endpoint.
- The startpoint can be an input, output, or I/O pin.
- The endpoint is always an output pin or an I/O pin.
- The only exception is a constraint timing arc, such as a setup or hold constraint between two input pins.
There are two timing arc types:
- combinational timing arc: combinational timing arc information is used to calculate the physical delays in timing propagation and to trace paths. The timing analyzer uses path-tracing arcs for circuit timing analysis.
- sequential timing arc: sequential timing arc information is used to determine rule-based design optimization constraints.