| period | setup/hold | uncertainty | applied to | add | |
| create_clock | √ | √ | node | second assignment will be ignored | |
| CREATE_GENERATED_CLOCK | √ | √ | node | ignore the new constraint and issue a warning | |
| DERIVE_PLL_CLOCKS | √ | √ | node | ||
| DERIVE_CLOCK_UNCERTAINTY | √ | Adds derived uncertainty to any uncertainties explicitly added by the user Overwrites the user's uncertainty, independent of order |
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| DERIVE_CLOCKS | |||||
| SET_CLOCK_GROUPS | √ | clock | |||
| SET_MULTICYCLE_PATH | √ | between keepers/clocks | |||
| GET_FANOUTS | |||||
| SET_MAX_DELAY/SET_MIN_DELAY | √ | between keepers/clocks | |||
| SET_FALSE_PATH | √ | between keepers/clocks | |||
| SET_CLOCK_UNCERTAINTY | √ | their uncertainty is additive to that calculated by derive_clock_uncertainty | |||
| SET_CLOCK_LATENCY | √ | ||||
| SET_INPUT_DELAY/SET_OUTPUT_DELAY | √ | node(external) | there is another external register connected to the port override the first two lines and a warning would be issued |
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| SET_MAX_SKEW | |||||