基于I2C EPPRPM（AT24C02B） + LCD12864实验

本次实验目的：在指定的EPPROM地址中，写入一数据，延时100MS后，在从该地址中读取，并在LCD上显示。

该实验在前两天就开始做了，一开始并没有成功，读出的一直0x00，当时也调了一会，但跳回到PS2鼠标实验继续调试（因为晚上睡觉会一直想那个问题），当把PS2鼠标实验调通之后，感觉自己对时序图有进一步的好感，写状态机时，我能抓住每一个动作细节，这就是经验吧，然后今天晚上调试I2C实验，直接对着时序图一步一步检查状态机的变动，经过仔细的检查，确实发现不少问题，当场就改掉，检查完一遍后（仅检查了一遍），改完后立即编译下载到板子上验证，结果很OK。此时我非常高兴，PS2鼠标实验花了那么长的时间去调试，是值得的。

由于主板子上没有EPPROM，故在外面用飞线接了一个AT24C02B器件，如下图。

在写代码前，建议先看看特权视频，有了一定的了解后，在去仔细的去琢磨I2C的时序。

1、首先得知道起始和停止在什么时候产生，

2、主机到设备发送数据时，是在时钟为低时改变数据，每发完一组数据，设备都会产生应答位。

3、主机从设备中读取数据时，是在时钟为高时进行锁存，因为在时钟高电平期间，SDA上的数据是稳定的，如果是连续读，每读完一组数据，主机一般要给设备发送应答位，读到最后一组数据时，主机可以不发送应答位，直接发送停止信号作为结束。

 

代码实现：

i2c_epprom.v

// 给EPPROM 写数据，延时100ms后读出该数据
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/ 1 ps
module i2c_epprom(
                    //input 
                    sys_clk,
                    rst_n,
                
                    //output
                    scl,
                    sda,   //inout
                    dis_data_low,
                    dis_data_hig
                );

input     sys_clk;                // 50MHz
input     rst_n;                    //复位信号，低有效
output     scl;                    // 24C02的时钟端口
inout     sda;                    // 24C02的数据端口
output [7:0] dis_data_low;        //LCD显示的数据
output [7:0] dis_data_hig;
/**************************************************************/
parameter     T100MS              =     23'd4_999_999;
parameter     IDLE              =     5'd0;
parameter     START1              =     5'd1;
parameter     ADD1              =     5'd2;
parameter     ACK1              =     5'd3;
parameter     ADD2              =     5'd4;
parameter     ACK2              =     5'd5;
parameter   WR_DATA          =     5'd6;
parameter    ACK2_1           =     5'd7;
parameter     STOP1              =     5'd8;
parameter   DELAY            =     5'd9;
parameter     START2              =     5'd10;
parameter     ADD3              =     5'd11;
parameter     ACK3             =     5'd12;
parameter   RD_DATA          =     5'd13;
parameter     ACK4             =     5'd14;
parameter     STOP2              =     5'd15;
parameter    OVER             =     5'd16;
/**************************************************************/
//100ms计数
reg [22:0] cnt1;
reg cnt_en;
always @ (posedge sys_clk or negedge rst_n)
if(!rst_n) 
    cnt1 <= 23'd0;
else if((!cnt_en) || (cnt1 == T100MS)) 
    cnt1 <= 23'd0;
else 
    cnt1 <= cnt1+1'b1;
/**************************************************************/
//分频部分
// cnt=0:scl上升沿，cnt=1:scl高电平中间，cnt=2:scl下降沿，cnt=3:scl低电平中间
reg[2:0] cnt;    
reg[8:0] cnt_delay;                            //500循环计数，产生iic所需要的时钟
reg scl_r;                                    //时钟脉冲寄存器
always @ (posedge sys_clk or negedge rst_n)
if(!rst_n) 
    cnt_delay <= 9'd0;
else if(cnt_delay == 9'd499) 
    cnt_delay <= 9'd0;                        //计数到10us为scl的周期，即100KHz
else 
    cnt_delay <= cnt_delay + 1'b1;            //时钟计数
/**************************************************************/
always @ (posedge sys_clk or negedge rst_n)
if(!rst_n) 
    cnt <= 3'd5;
else begin
    case (cnt_delay)
    9'd0      :     cnt <= 3'd0;                //cnt=0:scl上升沿
    9'd124    :    cnt <= 3'd1;                //cnt=1:scl高电平中间,用于数据采样
    9'd249    :    cnt <= 3'd2;                //cnt=2:scl下降沿
    9'd374    :    cnt <= 3'd3;                //cnt=3:scl低电平中间,用于数据变化
//    9'd499    :    cnt <= 3'd0;                //cnt=0:scl上升沿
    default    :     cnt <= 3'd5;
    endcase
end

/**************************************************************/
`define     SCL_POS            (cnt == 3'd0)        //cnt=0:scl上升沿
`define     SCL_HIG            (cnt == 3'd1)        //cnt=1:scl高电平中间,用于数据采样
`define     SCL_NEG            (cnt == 3'd2)        //cnt=2:scl下降沿
`define     SCL_LOW            (cnt == 3'd3)        //cnt=3:scl低电平中间,用于数据变化
/**************************************************************/        
`define        DEVICE_READ        8'b1010_0001 //被寻址器件地址（读操作）a1
`define     DEVICE_WRITE    8'b1010_0000 //被寻址器件地址（写操作）a0
`define        WRITE_DATA        8'hc8         //写入EEPROM的数据  
`define     BYTE_ADDR        8'h03          //写入/读出EEPROM的地址寄存器    
/**************************************************************/
always @ (posedge sys_clk or negedge rst_n)
if(!rst_n) 
    scl_r <= 1'b0;
else if(cnt_delay == 9'd0/*cnt==3'd0*/) 
    scl_r <= 1'b1;                            //scl信号上升沿
else if(cnt_delay == 9'd249/*cnt==3'd2*/) 
    scl_r <= 1'b0;                            //scl信号下降沿

assign scl = scl_r;                            //产生iic所需要的时钟
/**************************************************************/
reg [7:0] db_r;                                //在IIC上传送的数据寄存器
reg [7:0] read_data;                        //读出EEPROM的数据寄存器
reg [4:0] cstate;                            //状态寄存器
reg [3:0] num;
reg       sda_r;                            //输出数据寄存器
reg       sda_link;                            //输出数据sda信号inout方向控制位        
reg       rd_flag;                            //读操作标志
always @ (posedge sys_clk or negedge rst_n)
if(!rst_n) begin
    cstate <= IDLE;
    sda_r <= 1'b1;
    sda_link <= 1'b0;
    num <= 4'd0;
    rd_flag <= 1'b0;
    read_data <= 8'b0000_0000;
    cnt_en <= 1'b0;
end
else begin       
    case (cstate)
        IDLE:
        begin
            sda_link <= 1'b1;                //数据线sda为输出
            sda_r <= 1'b1;        
            cstate <= START1;        
            db_r <= `DEVICE_WRITE;            //送器件地址（写操作）
        end        
                
        START1:         
        begin        
            if(`SCL_HIG) begin                //scl为高电平期间
                num <= 4'd0;                //num计数清零
                sda_link <= 1'b1;            //数据线sda为output
                sda_r <= 1'b0;                //拉低数据线sda，产生起始位信号
                cstate <= ADD1;        
            end        
            else         
                cstate <= START1;             //等待scl高电平中间位置到来
        end        
                    
        ADD1:            
        begin                                  //给EPPROM送入器件地址
            if(`SCL_LOW) begin        
                if(num == 4'd8) begin        
                    num <= 4'd0;            //num计数清零
                    sda_r <= 1'b1;             
                    sda_link <= 1'b0;        //sda置为高阻态(input)
                    cstate <= ACK1;
                end
                else begin
                    sda_link <= 1'b1;
                    num <= num+1'b1;
                    case (num)
                    4'd0    :    sda_r <= db_r[7];
                    4'd1    :    sda_r <= db_r[6];
                    4'd2    :    sda_r <= db_r[5];
                    4'd3    :    sda_r <= db_r[4];
                    4'd4    :    sda_r <= db_r[3];
                    4'd5    :    sda_r <= db_r[2];
                    4'd6    :    sda_r <= db_r[1];
                    4'd7    :    sda_r <= db_r[0];
                    default    :                     ;
                    endcase
                    cstate <= ADD1;
                end
            end
            else 
                cstate <= ADD1;
        end
        ACK1: 
        begin
            if(`SCL_NEG) begin                //注：24C01/02/04/08/16器件可以不考虑应答位
                db_r <= `BYTE_ADDR;            // 1地址
                cstate <= ADD2;                //从机响应信号                    
            end
            else 
                cstate <= ACK1;                //等待从机响应
        end
             
        ADD2:    
        begin                               //给EPPROM送入存储地址
            if(`SCL_LOW) begin
                if(num==4'd8) begin    
                    num <= 4'd0;            //num计数清零
                    sda_r <= 1'b1;
                    sda_link <= 1'b0;        //sda置为高阻态(input)
                    cstate <= ACK2;
                end
                else begin
                    sda_link <= 1'b1;        //sda作为output
                    num <= num+1'b1;
                    case (num)
                    4'd0    :    sda_r <= db_r[7];
                    4'd1    :    sda_r <= db_r[6];
                    4'd2    :    sda_r <= db_r[5];
                    4'd3    :    sda_r <= db_r[4];
                    4'd4    :    sda_r <= db_r[3];
                    4'd5    :    sda_r <= db_r[2];
                    4'd6    :    sda_r <= db_r[1];
                    4'd7    :    sda_r <= db_r[0];
                    default    :                     ;
                    endcase        
                    cstate <= ADD2;                    
                end
            end
            else 
                cstate <= ADD2;                
        end
        
        ACK2: 
        begin
            if(`SCL_NEG) begin                //从机响应信号
                if(!rd_flag) begin
                    rd_flag <= 1'b1;          //标志下轮进入读状态                    
                    db_r <= `WRITE_DATA;    //写入的数据
                    cstate <= WR_DATA;         //写数据
                end
                else begin
                    rd_flag <= 1'b0;
                    cstate <= START2;
                end
            end
            else 
                cstate <= ACK2;                //等待从机响应
       end

        WR_DATA: 
        begin
            if(num<=4'd7) begin
                if(`SCL_LOW) begin
                    sda_link <= 1'b1;        //sda作为output
                    num <= num+1'b1;
                    case (num)
                    4'd0    :    sda_r <= db_r[7];
                    4'd1    :    sda_r <= db_r[6];
                    4'd2    :    sda_r <= db_r[5];
                    4'd3    :    sda_r <= db_r[4];
                    4'd4    :    sda_r <= db_r[3];
                    4'd5    :    sda_r <= db_r[2];
                    4'd6    :    sda_r <= db_r[1];
                    4'd7    :    sda_r <= db_r[0];
                    default    :                     ;
                    endcase
                    cstate <= WR_DATA;
                end
            end
            else if((`SCL_LOW) && (num==4'd8)) begin
                num <= 4'd0;
                sda_r <= 1'b1;
                sda_link <= 1'b0;            //sda置为高阻态
                cstate <= ACK2_1;
            end
        end
        
        ACK2_1: 
        begin
            if(`SCL_NEG)
                cstate <= STOP1;                    
            else 
                cstate <= ACK2_1;
        end
        
        STOP1:    
        begin
            if(`SCL_LOW) begin
                sda_link <= 1'b1;
                sda_r <= 1'b0;
                cstate <= STOP1;
            end
            else if(`SCL_HIG) begin
                sda_link <= 1'b1;
                sda_r <= 1'b1;                //scl为高时，sda产生上升沿（结束信号）
                cnt_en <= 1'b1;                //启动100MS计数器
                cstate <= DELAY;
            end
        end
        
        DELAY:                               //延时100ms后在进行读
        begin
            if(cnt1 == T100MS) begin
                cnt_en <= 1'b0;
                cstate <= IDLE;
            end
            else begin    
                sda_link <= 1'b1;
                sda_r <= 1'b1;
                cstate <= DELAY;
            end
        end
            
        START2: 
        begin                                //读操作起始位
            if(`SCL_LOW) begin
                sda_link <= 1'b1;            //sda作为output
                sda_r <= 1'b1;                //拉高数据线sda
                cstate <= START2;
            end
            else if(`SCL_HIG) begin            //scl为高电平中间
                num <= 4'd0;
                sda_link <= 1'b1;
                sda_r <= 1'b0;                //拉低数据线sda，产生起始位信号
                db_r <= `DEVICE_READ;          //准备读
                cstate <= ADD3;
            end     
            else 
                cstate <= START2;
        end
            
        ADD3:    
        begin                                //送器件地址 读操作
            if(`SCL_LOW) begin
                if(num==4'd8) begin    
                    num <= 4'd0;            //num计数清零
                    sda_r <= 1'b1;
                    sda_link <= 1'b0;        //sda置为高阻态(input)
                    cstate <= ACK3;
                end
                else begin
                    sda_link <= 1'b1;
                    num <= num+1'b1;
                    case (num)
                    4'd0    :    sda_r <= db_r[7];
                    4'd1    :    sda_r <= db_r[6];
                    4'd2    :    sda_r <= db_r[5];
                    4'd3    :    sda_r <= db_r[4];
                    4'd4    :    sda_r <= db_r[3];
                    4'd5    :    sda_r <= db_r[2];
                    4'd6    :    sda_r <= db_r[1];
                    4'd7    :    sda_r <= db_r[0];
                    default    :                     ;
                    endcase     
                    cstate <= ADD3;                    
                end
            end
            else cstate <= ADD3;                
        end
            
        ACK3:
        begin
            if(`SCL_NEG)
                cstate <= RD_DATA;            //从机响应信号
            else 
                cstate <= ACK3;             //等待从机响应
        end
        
        RD_DATA:
        begin
            if(num<=4'd7) begin
                if(`SCL_HIG) begin    
                    sda_link <= 1'b0;        // sda 作为输入管脚
                    num <= num+1'b1;    
                    case (num)
                    4'd0    :    read_data[7] <= sda;
                    4'd1    :    read_data[6] <= sda;  
                    4'd2    :    read_data[5] <= sda; 
                    4'd3    :    read_data[4] <= sda; 
                    4'd4    :    read_data[3] <= sda; 
                    4'd5    :    read_data[2] <= sda; 
                    4'd6    :    read_data[1] <= sda; 
                    4'd7    :    read_data[0] <= sda; 
                    default    :                         ;
                    endcase    
                    cstate <= RD_DATA;    
                end
                else
                    cstate <= RD_DATA;
            end
            else if((`SCL_LOW) && (num==4'd8)) begin
                num <= 4'd0;            //num计数清零
                sda_link <= 1'b1;
                sda_r <= 1'b0;           //数据拉低，准备产生停止信号
                cstate <= ACK4;          //这里也可以直接跳到STOP2
            end
            else
                cstate <= RD_DATA;
        end
        
        ACK4:                              //主机发出应答为
        begin
            if(`SCL_NEG) 
                cstate <= STOP2;                        
            else 
                cstate <= ACK4;
        end
        
        STOP2:
        begin
            if(`SCL_HIG) begin
                sda_link <= 1'b1;
                sda_r <= 1'b1;          //产生结束信号
                cstate <= OVER;
            end
            else
                cstate <= STOP2;
        end
        
        OVER: cstate <= OVER;
        
        default: cstate <= IDLE;
        
        endcase
end
/**************************************************************/
//sda_link =  1, 作为输出
//sda_link =  0, 作为输入，FPGA内部得把该管脚设置为高祖太，可以接收高低电平
assign sda = sda_link ? sda_r:1'bz; 
/**************************************************************/
reg [7:0] dis_data_low;
always @(read_data[3:0])
    case(read_data[3:0])
        4'h0: dis_data_low = "0";
        4'h1: dis_data_low = "1";
        4'h2: dis_data_low = "2";
        4'h3: dis_data_low = "3";
        4'h4: dis_data_low = "4";
        4'h5: dis_data_low = "5";
        4'h6: dis_data_low = "6";
        4'h7: dis_data_low = "7";
        4'h8: dis_data_low = "8";
        4'h9: dis_data_low = "9";
        4'ha: dis_data_low = "a";
        4'hb: dis_data_low = "b";
        4'hc: dis_data_low = "c";
        4'hd: dis_data_low = "d";
        4'he: dis_data_low = "e";
        4'hf: dis_data_low = "f";
    endcase
/**************************************************************/
reg [7:0] dis_data_hig;
always @(read_data[7:4])
    case(read_data[7:4])
        4'h0: dis_data_hig = "0";
        4'h1: dis_data_hig = "1";
        4'h2: dis_data_hig = "2";
        4'h3: dis_data_hig = "3";
        4'h4: dis_data_hig = "4";
        4'h5: dis_data_hig = "5";
        4'h6: dis_data_hig = "6";
        4'h7: dis_data_hig = "7";
        4'h8: dis_data_hig = "8";
        4'h9: dis_data_hig = "9";
        4'ha: dis_data_hig = "a";
        4'hb: dis_data_hig = "b";
        4'hc: dis_data_hig = "c";
        4'hd: dis_data_hig = "d";
        4'he: dis_data_hig = "e";
        4'hf: dis_data_hig = "f";
    endcase
/**************************************************************/
endmodule

LCD12864.v

module LCD12864(
                    //input 
                    sys_clk,
                    rst_n,
                    dis_data_low,
                    dis_data_hig,
                    
                    //output 
                    lcd_rs,
                    lcd_rw,
                    lcd_en,
                    lcd_data,
                    lcd_psb
                );
input sys_clk;// 50MHZ
input rst_n;
input [7:0] dis_data_low;
input [7:0] dis_data_hig;

output lcd_rs;//H:data    L:command
output lcd_rw;//H:read module    L:write module
output lcd_en;//H active
output [7:0] lcd_data;
output lcd_psb;//H:parallel    module    L:SPI module

/***************************************************/
parameter T3MS = 18'd149_999;
parameter    IDLE           = 5'd0,
            INIT_FUN_SET1 = 5'd1,
            INIT_FUN_SET2 = 5'd2,
            INIT_DISPLAY  = 5'd3,
            INIT_CLEAR       = 5'd4,
            INIT_DOT_SET  = 5'd5,
            SET_DDRAM      = 5'd6,
            WRITE_DATA0      = 5'd7,
            SET_DDRAM2    = 5'd8,
            WRITE_DATA1   = 5'd9,
            WRITE_DATA2   = 5'd10,
            WRITE_DATA3   = 5'd11;
            

/***************************************************/
//产生周期为6MS的lcd_clk给LCD
reg [17:0] cnt;
reg lcd_clk;
always @(posedge sys_clk or negedge rst_n)
if(!rst_n) begin
    cnt <= 18'd0;
    lcd_clk <= 1'b0;
end
else if(cnt == T3MS)begin
    cnt <= 18'd0;
    lcd_clk <= ~lcd_clk;
end
else
    cnt <= cnt + 1'b1;

/***************************************************/
reg lcd_rs;
reg [4:0] state;
always @(posedge lcd_clk or negedge rst_n)
if(!rst_n)
    lcd_rs <= 1'b0;
else if((state == WRITE_DATA0)  || (state == WRITE_DATA1) 
        || (state == WRITE_DATA2)  || (state == WRITE_DATA3))
    lcd_rs <= 1'b1;        //写数据模式
else
    lcd_rs <= 1'b0;        //写命令模式
/***************************************************/
reg [7:0] lcd_data;
reg [7:0] dis_data;
reg [6:0] num;
reg en;
always @(posedge lcd_clk or negedge rst_n)
if(!rst_n) begin
    state <= IDLE;
    lcd_data <= 8'h00;
    en <= 1'b1;
    num <= 7'd0;
end    
else 
    case(state)
        IDLE: 
        begin
            state <= INIT_FUN_SET1;
            lcd_data <= 8'hzz;
            en <= 1'b1;
        end
        
        INIT_FUN_SET1: 
        begin
            lcd_data <= 8'h30;    //功能设定
            state <= INIT_FUN_SET2;
        end 
        
        INIT_FUN_SET2:
        begin
            lcd_data <= 8'h30;    //功能设定
            state <= INIT_DISPLAY;
        end
            
        INIT_DISPLAY:
        begin
            lcd_data <= 8'h0c;    //显示设定
            state <= INIT_CLEAR;
        end
            
        INIT_CLEAR:
        begin
            lcd_data <= 8'h01;    //清屏
            state <= INIT_DOT_SET;
        end
        
        INIT_DOT_SET:
        begin
            lcd_data <= 8'h06;    //进入点设定
            state <= SET_DDRAM;
        end
        
        SET_DDRAM:
        begin
            lcd_data <= 8'h91;//2 line            
            state <= WRITE_DATA0;
        end
        
        WRITE_DATA0:  ////I2C通信实验
        begin
            if(num == 7'd11)
                state <= SET_DDRAM2;
            else begin
                num <= num + 1'b1;
                lcd_data <= dis_data;
                state <= WRITE_DATA0;  
            end
        end
        
        SET_DDRAM2:
        begin
            lcd_data <= 8'h89;//3 line            
            state <= WRITE_DATA1;
        end
        
        WRITE_DATA1:  //03地址值
        begin
            if(num == 7'd20) begin
                num <= 7'd0;
                state <= WRITE_DATA2;
            end
            else begin
                num <= num + 1'b1;
                lcd_data <= dis_data;
                state <= WRITE_DATA1;  
            end
        end
        
        WRITE_DATA2: //高字节
        begin
            lcd_data <= dis_data_hig;
            state <= WRITE_DATA3;  
        end
        
        WRITE_DATA3://低字节
        begin
            lcd_data <= dis_data_low;
            state <= SET_DDRAM;  
        end

/*        STOP: 
        begin
            en <= 1'b0;//显示完了，lcd_e就一直拉为低
            state <= STOP;
        end   */
        
        default: state <= IDLE;
    endcase


always @(posedge sys_clk or negedge rst_n)
if(!rst_n)
    dis_data <= 8'h00;
else
    case(num)
    //I2C通信实验%CD%A8%D0%C5%CA%B5%D1%E9
    7'd0   :    dis_data <= "I";
    7'd1   :    dis_data <= "2"; 
    7'd2   :    dis_data <= "C";
    7'd3   :    dis_data <= " ";//8'hcd;
    7'd4   :    dis_data <= "E";//8'ha8;
    7'd5   :    dis_data <= "P";//8'hd0;
    7'd6   :    dis_data <= "P";//8'hc5;
    7'd7   :    dis_data <= "R";//8'hca;
    7'd8   :    dis_data <= "O";//8'hb5;
    7'd9   :    dis_data <= "M";//8'hd1;
    7'd10  :    dis_data <= " ";//8'he9;
    //03地址值 %B5%D8%D6%B7
    7'd11  :    dis_data <= "0";
    7'd12  :    dis_data <= "3";
    7'd13  :    dis_data <= 8'hb5;
    7'd14  :    dis_data <= 8'hd8; 
    7'd15  :    dis_data <= 8'hd6; 
    7'd16  :    dis_data <= 8'hb7; 
    7'd17  :    dis_data <= 8'hd6;
    7'd18  :    dis_data <= 8'hb5;
    7'd19  :    dis_data <= " ";
    default:    dis_data <= 8'h00;
    endcase
/***************************************************/
assign lcd_rw = 1'b0;//只有写模式
assign lcd_psb = 1'b1;//并口模式
assign lcd_en = en ?  lcd_clk : 1'b0;
/***************************************************/
endmodule

i2c_top.v

module i2c_top(
                //input 
                sys_clk,
                rst_n,
                
                //inout
                sda,
                
                //output
                scl,
                lcd_rs,
                lcd_rw,
                lcd_en,
                lcd_data,
//                lcd_psb
                );
input sys_clk;        // 50MHz
input rst_n;    //复位信号，低有效
output scl;        // 24C02的时钟端口
inout sda;        // 24C02的数据端口

output lcd_rs;//H:data    L:command
output lcd_rw;//H:read module    L:write module
output lcd_en;//H active
output [7:0] lcd_data;
//output lcd_psb;//H:parallel    module    L:SPI module
wire [7:0] dis_data_low;
wire [7:0] dis_data_hig;

i2c_epprom    u1(
                        //input 
                        .sys_clk(sys_clk),
                        .rst_n(rst_n),
                    
                        //output
                        .scl(scl),
                        .sda(sda),
                        .dis_data_low(dis_data_low),
                        .dis_data_hig(dis_data_hig)
                    );
                    
LCD12864        u2(
                        //input 
                        .sys_clk(sys_clk),
                        .rst_n(rst_n),
                        .dis_data_low(dis_data_low),
                        .dis_data_hig(dis_data_hig),
                        
                        //output 
                        .lcd_rs(lcd_rs),
                        .lcd_rw(lcd_rw),
                        .lcd_en(lcd_en),
                        .lcd_data(lcd_data)
//                        .lcd_psb(lcd_psb)
                        );
endmodule

OK,先到这，明天在完善吧。。。。