dra7xx MPU 调整：
1. Uboot the patches as below:
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index ae25a74..d062708 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -42,7 +42,7 @@ static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
/* OPP NOM FREQUENCY for OMAP5 ES2.0, and DRA7 ES1.0 */
static const struct dpll_params mpu_dpll_params_1ghz[NUM_SYS_CLKS] = {
{250, 2, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
- {500, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
+ {400, 9, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 20 MHz */
{119, 1, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
{625, 11, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
{500, 12, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
@@ -718,7 +718,7 @@ const struct ctrl_ioregs ioregs_dra72x_es2 = {
2. kernel: the patches as below:
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 4fa2eed..852f74a 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -102,8 +102,8 @@
compatible = "operating-points-v2";
opp-shared;
- opp_nom@1000000000 {
- opp-hz = /bits/ 64 <1000000000>;
+ opp_nom@800000000 {
+ opp-hz = /bits/ 64 <800000000>;
opp-microvolt = <1060000 850000 1150000>;
opp-supported-hw = <0xFF 0x01>;
opp-suspend;
3. test
1. mhz
root@dra7xx-evm:~# mhz
800 MHz, 1.2500 nanosec clock
2.get cur
root@dra7xx-evm:~# cat /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_cur_freq
800000
for multi operation point:
please remove more point, leaving one point can work.