xapp1151_Param_CAM模块安装
所需生成模块
- TCAM
- CAM
下载链接
赛灵思技术支持网站：http://www.xilinx.com/support.html
并在网页中搜索xapp1151，下载xapp1151_Param_CAM.zip，如下图所示
安装过程
1、在任意一个目录下，解压xapp1151_Param_CAM.zip
unzip xapp1151_Param_CAM.zip
并将reference_router_nf1_cml文件下的patches文件夹复制到刚刚解压的xapp1151_Param_cam目录下
cp -r patches <path>/xapp1151_cam_v1_1/
然后需添加一下ISE的路径信息
source <ISE_POSIZITION>/ISE_DS/settings64.sh
然后进入patches目录执行cam_patch.sh文件，打一些补丁
cd <path>/xapp1151_cam_v1_1/patches/
sh cam_patch.sh
笔者这里遇到了一个问题，错误提示如下
wpq@wpq:~/Downloads/xapp1151_cam_v1_1/patches$ sh cam_patch.sh
Invalid file name ../implement/CustomizeWrapper.pl -- skipping patch
Invalid file name ../implement/vhdl_xst.scr -- skipping patch
Invalid file name ../src/vhdl/cam_pkg.vhd -- skipping patch
Invalid file name ../src/vhdl/cam_control.vhd -- skipping patch
Invalid file name ../src/vhdl/cam_mem_blk.vhd -- skipping patch
Invalid file name ../src/vhdl/cam_mem_blk_extdepth_prim.vhd -- skipping patch
Invalid file name ../src/vhdl/cam_rtl.vhd -- skipping patch
查看了问题缺少了文件，笔者也觉得很纳闷，于是尝试着修改cam_patch.sh把这相对路径改成绝对路径，如下
patch /home/wpq/Downloads/xapp1151_cam_v1_1/implement/CustomizeWrapper.pl CustomizeWrapper.pl.patch
patch /home/wpq/Downloads/xapp1151_cam_v1_1/implement/vhdl_xst.scr vhdl_xst.scr.patch
patch /home/wpq/Downloads/xapp1151_cam_v1_1/src/vhdl/cam_pkg.vhd cam_pkg.vhd.patch
patch /home/wpq/Downloads/xapp1151_cam_v1_1/src/vhdl/cam_control.vhd cam_control.vhd.patch
patch /home/wpq/Downloads/xapp1151_cam_v1_1/src/vhdl/cam_mem_blk.vhd cam_mem_blk.vhd.patch
patch /home/wpq/Downloads/xapp1151_cam_v1_1/src/vhdl/cam_mem_blk_extdepth_prim.vhd cam_mem_blk_extdepth_prim.vhd.patch
patch /home/wpq/Downloads/xapp1151_cam_v1_1/src/vhdl/cam_rtl.vhd cam_rtl.vhd.patch
此时在执行cam_patch.sh文件成功解决，如下
wpq@wpq:~/Downloads/xapp1151_cam_v1_1/patches$ sh cam_patch.sh
patching file /home/wpq/Downloads/xapp1151_cam_v1_1/implement/vhdl_xst.scr
patching file /home/wpq/Downloads/xapp1151_cam_v1_1/src/vhdl/cam_pkg.vhd
patching file /home/wpq/Downloads/xapp1151_cam_v1_1/src/vhdl/cam_control.vhd
patching file /home/wpq/Downloads/xapp1151_cam_v1_1/src/vhdl/cam_mem_blk.vhd
patching file /home/wpq/Downloads/xapp1151_cam_v1_1/src/vhdl/cam_mem_blk_extdepth_prim.vhd
patching file /home/wpq/Downloads/xapp1151_cam_v1_1/src/vhdl/cam_rtl.vhd
2、CAM模块生成
执行以下命令，并填入如下所示参数：
cd <path>/xapp1151_cam_v1_1/implement
xilperl CustomizeWrapper.pl
You need to specify several parameters. To choose those options, see follows:
***************************************************************
CAM Reference Design Customizer v1.1
***************************************************************
***************************************************************
Please input the following parameters for the CAM:
***************************************************************
Enter the FPGA base architecture to target
Valid options are virtex4, virtex5, virtex6, virtex6l, spartan3, spartan3e, spartan3a, spartan3adsp, aspartan3, aspartan3e, spartan6, kintex7 :
kintex7
Input the CAM data width. Valid values are 1-512:
32
Input the CAM depth. Valid values are 16-4096:
32
Enter the CAM memory type to implement
(Choose SRL-based if you need a Ternary or Enhanced Ternary mode CAM)
0 = SRL-based, 1 = BRAM-based: 0
Choose the Ternary Mode setting.
0 = Ternary Mode Off, 1 = Standard Ternary Mode, 2 = Enhanced Ternary Mode: 1
Will the CAM be write-able (WE pin)? (If no, CAM will be read-only) (y/n): y
Use a MIF file to initialize the memory contents? (y/n): n
Choose what type of encoding the MATCH_ADDR port will have.
0 = Binary Encoded, 1 = Single Match Unencoded (one-hot), 2 = Multi-match Unencoded: 1
For Binary Encoded or Single Match Unencoded MATCH_ADDR, output lowest address match or highest address match?
0 = Lowest, 1 = Highest: 0
Please select the optional features to be implemented:
Simultaneous Read/Write (y/n): y
Please select from the following optional input ports:
Enable (EN) (y/n): n
Please select from the following optional output ports:
Multiple Match Flag (MULTIPLE_MATCH) (y/n): n
Single Match Flag (SINGLE_MATCH) (y/n): n
Read Warning Flag (READ_WARNING) (y/n): n
After the selections the parameters should be as follows:
VHDL parameters were generated as follows:
===============================================
C_FAMILY : string := kintex7;
C_MEM_TYPE : integer := 0;
C_WIDTH : integer := 32;
C_DEPTH : integer := 32;
C_ADDR_TYPE : integer := 1;
C_MATCH_RESOLUTION_TYPE : integer := 0;
C_TERNARY_MODE : integer := 1;
C_HAS_WE : integer := 1;
C_MEM_INIT : integer := 0;
C_HAS_CMP_DIN : integer := 1;
C_REG_OUTPUTS : integer := 0;
C_HAS_EN : integer := 0;
C_HAS_MULTIPLE_MATCH : integer := 0;
C_HAS_SINGLE_MATCH : integer := 0;
C_HAS_READ_WARNING : integer := 0;
===============================================
查看相同目录下的vhdl_xst.scr文件，并将-ofn ./results/cam.ngc改成```-ofn ./results/tcam.ngc``，如下所示
run
-ifmt VHDL
-work_lib cam
-p xc7k325tffg676-1
-write_timing_constraints No
-ifn vhdl_xst.prj
-iobuf NO
-max_fanout 100
-ofn ./results/tcam.ngc
-ofmt NGC
-bufg 1
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
-opt_mode Speed
-opt_level 1
-loop_iteration_limit 5000
-use_new_parser yes
然后执行
xilperl RunXST.pl
3、修改Verilog代码
执行以下命令，生成对应的verilog代码
cd results
netgen -sim -ofmt verilog tcam.ngc
修改生成的tcam.v文件
-
将代码中的模块名
cam_wrapper改成tcam -
在端口声明后（即在output下一句，wire上一句），加入以下语句，虽然此句为注释，但必须得加上去，不然后续步骤会报错，笔者亲身踩坑
// synthesis translate_off -
在cam_wrapper(上面我们已经改名为tcam)的endmodule前面加入以下语句
// synthesis translate_on
4、将生成的文件复制到NetFPGA-1G-CML-live的相应目录下
执行以下命令，创建netlist目录
mkdir -p $(NF10_ROOT_DIRECTORY)/lib/hw/std/pcores/nf10_router_output_port_lookup_v1_00_a/netlist
将tcam.ngc复制到刚刚创建的netlist目录
cp tcam.ngc $(NF_ROOT)/lib/hw/std/pcores/nf10_router_output_port_lookup_v1_00_a/netlist
将tcam.v复制到对应的verilog目录下
cp tcam.v $(NF_ROOT)/lib/hw/std/pcores/nf10_router_output_port_lookup_v1_00_a/hdl/verilog
5、生成第二个cam模块，具体步骤与上述1-4步骤相似，只是一些参数不同
xilperl CustomizeWrapper.pl
You need to specify several parameters. To choose those options, see follows:
***************************************************************
CAM Reference Design Customizer v1.1
***************************************************************
***************************************************************
Please input the following parameters for the CAM:
***************************************************************
Enter the FPGA base architecture to target
Valid options are virtex4, virtex5, virtex6, virtex6l, spartan3, spartan3e, spartan3a, spartan3adsp, aspartan3, aspartan3e, spartan6, kintex7 :
kintex7
Input the CAM data width. Valid values are 1-512:
32
Input the CAM depth. Valid values are 16-4096:
32
Enter the CAM memory type to implement
(Choose SRL-based if you need a Ternary or Enhanced Ternary mode CAM)
0 = SRL-based, 1 = BRAM-based: 1
NOTE: BRAM-based CAMs do not support Ternary Modes.
Setting C_TERNARY_MODE = 0 ...
Will the CAM be write-able (WE pin)? (If no, CAM will be read-only) (y/n): y
Use a MIF file to initialize the memory contents? (y/n): n
Choose what type of encoding the MATCH_ADDR port will have.
0 = Binary Encoded, 1 = Single Match Unencoded (one-hot), 2 = Multi-match Unencoded: 1
For Binary Encoded or Single Match Unencoded MATCH_ADDR, output lowest address match or highest address match?
0 = Lowest, 1 = Highest: 0
Please select the optional features to be implemented:
Simultaneous Read/Write (y/n): y
Register Outputs (y/n): n
Please select from the following optional input ports:
Enable (EN) (y/n): n
Please select from the following optional output ports:
Multiple Match Flag (MULTIPLE_MATCH) (y/n): n
Single Match Flag (SINGLE_MATCH) (y/n): n
Read Warning Flag (READ_WARNING) (y/n): n
After the selections the parameters should be as follows:
VHDL parameters were generated as follows:
===============================================
C_FAMILY : string := kintex7;
C_MEM_TYPE : integer := 1;
C_WIDTH : integer := 32;
C_DEPTH : integer := 32;
C_ADDR_TYPE : integer := 1;
C_MATCH_RESOLUTION_TYPE : integer := 0;
C_TERNARY_MODE : integer := 0;
C_HAS_WE : integer := 1;
C_MEM_INIT : integer := 0;
C_HAS_CMP_DIN : integer := 1;
C_REG_OUTPUTS : integer := 0;
C_HAS_EN : integer := 0;
C_HAS_MULTIPLE_MATCH : integer := 0;
C_HAS_SINGLE_MATCH : integer := 0;
C_HAS_READ_WARNING : integer := 0;
===============================================
修改vhdl_xst.scr文件，如下所示
run
-ifmt VHDL
-work_lib cam
-p xc7k325tffg676-1
-write_timing_constraints No
-ifn vhdl_xst.prj
-iobuf NO
-max_fanout 100
-ofn ./results/cam.ngc
-ofmt NGC
-bufg 1
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
-opt_mode Speed
-opt_level 1
-loop_iteration_limit 5000
-use_new_parser yes
然后执行
xilperl RunXST.pl
生成verilog代码
cd results
netgen -sim -ofmt verilog cam.ngc
修改verilog代码
-
将代码中的模块名
cam_wrapper改成cam -
在端口声明后（即在output下一句，wire上一句），加入以下语句，虽然此句为注释，但必须得加上去，不然后续步骤会报错，笔者亲身踩坑
// synthesis translate_off -
在cam_wrapper(上面我们已经改名为tcam)的endmodule前面加入以下语句
// synthesis translate_on
复制文件
cp cam.ngc $(NF_ROOT)/lib/hw/std/pcores/nf10_router_output_port_lookup_v1_00_a/netlist
cp cam.v $(NF_ROOT)/lib/hw/std/pcores/nf10_router_output_port_lookup_v1_00_a/hdl/verilog