Verilog-分频器

一、占空比50%的奇数分频

1、实现思路

　　实现奇数（N）分频，分别用上升沿计数到（N-1)/2，再计数到N-1；用下降沿计数到（N-1)/2，再计数到N-1，得到两个波形，然后把它们相或即可得到N分频。

2、代码

module fp_odd(clk_in,rst_n,cnt_p,cnt_n,clk_p,clk_n,clk_out);
parameter N=5;
input clk_in;
input rst_n;
output[2:0] cnt_p;
output[2:0] cnt_n;
output clk_p;
output clk_n;
output clk_out;

reg[2:0] cnt_p;
reg[2:0] cnt_n;
reg clk_p;
reg clk_n;

always @(posedge clk_in or negedge rst_n)
begin
    if(!rst_n) cnt_p <= 0;
    else 
    begin
        if(cnt_p == N-1) cnt_p <= 0;
        else cnt_p <= cnt_p + 1'b1;
    end
end

always @(posedge clk_in or negedge rst_n)
begin
    if(!rst_n) clk_p <= 0;
    else
    begin
        if(cnt_p == (N-1)/2) clk_p <= !clk_p;
        else if(cnt_p == N-1) clk_p <= !clk_p;
        else clk_p <= clk_p;
    end
end

always @(negedge clk_in or negedge rst_n)
begin
    if(!rst_n) cnt_n <= 0;
    else 
    begin
        if(cnt_n == N-1) cnt_n <= 0;
        else cnt_n <= cnt_n + 1'b1;
    end
end

always @(negedge clk_in or negedge rst_n)
begin
    if(!rst_n) clk_n <= 0;
    else
    begin
        if(cnt_n == (N-1)/2) clk_n <= !clk_n;
        else if(cnt_n == N-1) clk_n <= !clk_n;
        else clk_n <= clk_n;
    end
end

assign clk_out = clk_p | clk_n;

endmodule

3、仿真波形