基于Verilog的串口接收程序

一、模块框图及基本思路

detect_module:检测输入引脚的下降沿，以此判断一帧数据的开始

rx_bps_module:波特率时钟产生模块

rx_control_module:串口接收的核心控制模块

rx_module:前三个模块的组合

control_module2:接受控制模块，不断接收串口数据

rx_top_module:将接收到数据的第四位以LED的形式显示

二、软件部分

detect_module：

module detect_module(
    CLK,RSTn,
    RX_Pin_in,
    H2L_Sig
    );
     input CLK,RSTn;
     input RX_Pin_in;
     output H2L_Sig;
     
     /**********************************/
     reg RX_r1;
     reg RX_r2;
     
     always @(posedge CLK or negedge RSTn)
     begin
        if(!RSTn)
        begin
            RX_r1<=1'b1;
            RX_r2<=1'b1;
        end
        else 
        begin
            RX_r1<=RX_Pin_in;
            RX_r2<=RX_r1;
        end
     end
     /*********************************/
     
     assign H2L_Sig=RX_r2&(!RX_r1);
     


endmodule

rx_bps_module：

module rx_bps_module #(parameter Baud=9600)(
    CLK,RSTn,
    Count_Sig,
    BPS_CLK
    );
    input CLK;
    input RSTn;
    input Count_Sig;
    output BPS_CLK;
    
    /***************************/
    localparam Baud_Div=50_000_000/Baud-1;
    localparam Baud_Div2=Baud_Div/2;
    
    reg[15:0] Count_BPS;
    /*************************/
    always @(posedge CLK or negedge RSTn)
    begin
        if(!RSTn)
            Count_BPS<=16'd0;
        else if(Count_BPS==Baud_Div)
            Count_BPS<=16'd0;
        else if(Count_Sig)
            Count_BPS<=Count_BPS+1;
        else Count_BPS<=16'd0;
    end
    /************************/
    assign BPS_CLK=(Count_BPS==Baud_Div2)?1'b1:1'b0;
endmodule

rx_control_module：

module rx_control_module(
    CLK,RSTn,
    H2L_Sig,BPS_CLK,RX_Pin_in,
    Count_Sig,RX_En_Sig,RX_Done_Sig,RX_Data
    );
     
     input CLK,RSTn;
     input H2L_Sig,BPS_CLK,RX_En_Sig,RX_Pin_in;
     output Count_Sig,RX_Done_Sig;
     output [7:0] RX_Data;
     
     reg[3:0] i;
     reg isCount;
     reg isDone;
     reg [7:0] rData;
     /********************************************/
     always @(posedge CLK or negedge RSTn)
     begin
        if(!RSTn)
        begin
            i<=4'd0;
            isCount<=1'b0;
            isDone<=1'b0;
            rData<=8'd0;
        end
        else if(RX_En_Sig)
        begin
            case(i)
            4'd0:if(H2L_Sig) begin i<=i+1'b1;isCount<=1'b1; end   //接收到下降沿开始启动波特率计数
            4'd1:if(BPS_CLK) begin i<=i+1'b1; end                 //起始位
            4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8,4'd9:
            if(BPS_CLK) begin rData[i-2]<=RX_Pin_in;i<=i+1'b1;end  //数据位
            4'd10:if(BPS_CLK) begin i<=i+1'b1; end                 //校验位
            4'd11:if(BPS_CLK) begin i<=i+1'b1; end                 //停止位
            4'd12:if(BPS_CLK) begin i<=i+1'b1;isDone<=1'b1;isCount<=1'b0; end       //一个时钟脉冲的 isDone 信号 
            4'd13:begin i<=1'b0;isDone<=1'b0; end
            endcase
        end
     
     end
     
     /********************************************/
     assign Count_Sig=isCount;
     assign RX_Done_Sig=isDone;
     assign RX_Data=rData;


endmodule

rx_module:

module rx_module(
    CLK,RSTn,
    RX_Pin_in,RX_Done_Sig,RX_Data,RX_En_Sig
    );
    
    input CLK,RSTn;
    input RX_Pin_in,RX_En_Sig;
    output RX_Done_Sig;
    output [7:0] RX_Data;
    
    wire Count_Sig;
    wire BPS_CLK;
    wire H2L_Sig;
    
    
    rx_bps_module U0(
    .CLK(CLK),.RSTn(RSTn),
    .Count_Sig(Count_Sig),
    .BPS_CLK(BPS_CLK)
    );
     
    detect_module U1(
     .CLK(CLK),.RSTn(RSTn),
     .RX_Pin_in(RX_Pin_in),
     .H2L_Sig(H2L_Sig)
    );
     
    rx_control_module U2(
     .CLK(CLK),.RSTn(RSTn),
     .H2L_Sig(H2L_Sig),.BPS_CLK(BPS_CLK),.RX_Pin_in(RX_Pin_in),
     .Count_Sig(Count_Sig),.RX_En_Sig(RX_En_Sig),.RX_Done_Sig(RX_Done_Sig),.RX_Data(RX_Data)
    );

endmodule

control_module2：

module control_module2(
    CLK,RSTn,
    RX_Done_Sig,
    RX_En_Sig,
    RX_Data,
    Number_Data
    );
     
     input CLK;
     input RSTn;
     input RX_Done_Sig;
     input [7:0]RX_Data;
     output RX_En_Sig;
     output [7:0] Number_Data;
     
     /***************************************/
     reg[7:0] rData;
     reg rEn;
     always @(posedge CLK or negedge RSTn)
     begin
        if(!RSTn)
        begin
            rData<=8'd0;
            rEn<=1'b0;
        end
        else if(RX_Done_Sig)
        begin
            rEn<=1'b0;
            rData<=RX_Data;
        end
        else rEn<=1'b1;
     end
     /***************************************/
    assign Number_Data=rData;
    assign RX_En_Sig=rEn;

endmodule

rx_top_module：

module rx_top_module(
    CLK,RSTn,
    RX_Pin_in,Led
    );
    input CLK,RSTn;
    input RX_Pin_in;
    output [3:0]Led;
    
    wire RX_Done_Sig;
    wire RX_En_Sig;
    wire [7:0] Number_Data;
    wire [7:0] RX_Data;
    
    rx_module U0(
    .CLK(CLK),.RSTn(RSTn),
    .RX_Pin_in(RX_Pin_in),.RX_Done_Sig(RX_Done_Sig),.RX_Data(RX_Data),.RX_En_Sig(RX_En_Sig)
    );
     
    control_module2 U1(
     .CLK(CLK),.RSTn(RSTn),
     .RX_Done_Sig(RX_Done_Sig),
     .RX_En_Sig(RX_En_Sig),
     .RX_Data(RX_Data),
     .Number_Data(Number_Data)
    );

    assign Led=Number_Data[3:0];
endmodule

三、硬件部分

黑金SPARTAN-6开发板

NET "CLK" LOC = T8;
NET "RSTn" LOC = L3;
NET "RX_Pin_in" LOC = C11;
NET "Led[0]" LOC = P4;
NET "Led[1]" LOC = N5;
NET "Led[2]" LOC = P5;
NET "Led[3]" LOC = M6;