基于Verilog的串口发送程序

一、模块框图及基本思路

tx_bps_module:波特率时钟产生模块

tx_control_module:串口发送的核心控制模块

tx_module:前两个模块的组合

control_module:发送控制模块，每秒触发一次发送

tx_top_module:tx_module+control_module

二、软件部分

tx_bps_module:

module tx_bps_module #(parameter Baud=9600)(
    CLK,RSTn,
    Count_Sig,
    BPS_CLK
    );
    input CLK;
    input RSTn;
    input Count_Sig;
    output BPS_CLK;
    
    /***************************/
    localparam Baud_Div=50_000_000/Baud-1;
    localparam Baud_Div2=Baud_Div/2;
    
    reg[15:0] Count_BPS;
    /*************************/
    always @(posedge CLK or negedge RSTn)
    begin
        if(!RSTn)
            Count_BPS<=16'd0;
        else if(Count_BPS==Baud_Div)
            Count_BPS<=16'd0;
        else if(Count_Sig)
            Count_BPS<=Count_BPS+1;
        else Count_BPS<=16'd0;
    end
    /************************/
    assign BPS_CLK=(Count_BPS==Baud_Div2)?1'b1:1'b0;
endmodule

tx_control_module:

module tx_control_module(
    CLK,RSTn,
    TX_En_Sig,TX_Data,BPS_CLK,
    TX_Done_Sig,TX_Pin_Out
    );
    input CLK,RSTn;
    input TX_En_Sig,BPS_CLK;
    input [7:0]TX_Data;
    output TX_Done_Sig,TX_Pin_Out;
    /***************************************/
    reg rTX;
    reg isDone;
    reg[3:0] i; 
    always @(posedge CLK or negedge RSTn)
    begin
        if(!RSTn)
        begin
            rTX<=1'b1;
            isDone<=1'b0;
            i<=4'd0;
        end
        else if(TX_En_Sig)
        begin
            case(i)
            4'd0:if(BPS_CLK) begin rTX<=0;i<=i+1'b1; end
            4'd1,4'd2,4'd3,4'd4,4'd5,4'd6,4'd7,4'd8:
            if(BPS_CLK) begin rTX<=TX_Data[i-1];i<=i+1'b1; end
            4'd9:if(BPS_CLK) begin rTX<=1;i<=i+1'b1; end
            4'd10:if(BPS_CLK) begin rTX<=1;i<=i+1'b1; end
            4'd11:if(BPS_CLK) begin isDone<=1;i<=i+1'b1; end
            4'd12: begin isDone<=0;i<=1'b0; end
            endcase
        end
    end
    /***************************************/
    assign TX_Pin_Out=rTX;
    assign TX_Done_Sig=isDone;
endmodule

tx_module:

module tx_module(
    CLK,RSTn,
    TX_En_Sig,TX_Data,TX_Pin_Out,TX_Done_Sig
    );
    input CLK;
    input RSTn;
    input TX_En_Sig;
    input [7:0] TX_Data;
    output TX_Pin_Out;
    output TX_Done_Sig;
    
    wire BPS_CLK;
    
    tx_bps_module U0(.CLK(CLK),.RSTn(RSTn),.Count_Sig(TX_En_Sig),.BPS_CLK(BPS_CLK));
    tx_control_module U1(.CLK(CLK),.RSTn(RSTn),.TX_En_Sig(TX_En_Sig),
                    .BPS_CLK(BPS_CLK),.TX_Data(TX_Data),.TX_Done_Sig(TX_Done_Sig),
                    .TX_Pin_Out(TX_Pin_Out));
endmodule

control_module:

module control_module(
   CLK, RSTn,
   TX_Done_Sig,
   TX_En_Sig, TX_Data
    );
    input CLK;
    input RSTn;
    input TX_Done_Sig;
    output TX_En_Sig;
    output [7:0]TX_Data;
    
    /***********************************************/
    localparam T1S=26'd49_999_99;
    reg [25:0] Count_Sec;
    always @(posedge CLK or negedge RSTn)
    begin
        if(!RSTn)
            Count_Sec<=26'd0;
        else if(Count_Sec==T1S) Count_Sec<=26'd0;
        else Count_Sec<=Count_Sec+1'b1;
    end
    /************************************************/
    
    reg[7:0] rData;
    reg isEn;
    always @(posedge CLK or negedge RSTn)
    begin
        if(!RSTn)
        begin
            rData<=8'h31;
            isEn<=1'b0;
        end
        else if(TX_Done_Sig)
        begin
            rData<=8'h31;
            isEn<=1'b0;
        end
        else if(Count_Sec==T1S) isEn<=1'b1;
    end
    
    /*************************************************/
    assign TX_Data=rData;
    assign TX_En_Sig=isEn;
    
    /*************************************************/
endmodule

tx_top_module:

module tx_top_module(
    CLK,RSTn,
    TX_Pin_Out
    );
    input CLK;
    input RSTn;
    output TX_Pin_Out;
    
    wire TX_Done_Sig;
    wire TX_En_Sig;
    wire [7:0]TX_Data;
    control_module U0(
      .CLK(CLK), .RSTn(RSTn),
      .TX_Done_Sig(TX_Done_Sig),
      .TX_En_Sig(TX_En_Sig), .TX_Data(TX_Data));
      
    tx_module U1(
      .CLK(CLK),.RSTn(RSTn),
      .TX_En_Sig(TX_En_Sig),.TX_Data(TX_Data),.TX_Pin_Out(TX_Pin_Out),.TX_Done_Sig(TX_Done_Sig)
     );
endmodule

三、硬件部分

黑金SPARTAN开发板

NET "CLK" LOC = T8;
NET "RSTn" LOC = L3;
NET "TX_Pin_Out" LOC = D12;