通过P1.0输出ACLK,P1.4输出SMCLK
1 int main(void) { 2 volatile unsigned int i; // Volatile to prevent removal 3 4 WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer 5 6 /* 7 BCSCTL3 |= LFXT1S_2; // LFXT1 = VLO 低频时钟选择为VLO ACLK选为VLO 8 9 IFG1 &= ~OFIFG; // Clear OSCFault flag 清除振荡器错误中断标志 10 11 __bis_SR_register(SCG1 + SCG0); // Stop DCO SCG1禁止SMCLK SCG0禁止DCO 12 13 BCSCTL2 |= SELM_3 + DIVM_3; // MCLK = LFXT1/8 14 15 //因为前面已经选择了LFXT1 = VLO 所以MCLK选为VLO 8分频 所以CPU的MCLK大约为1.5KHz 16 * //VLO典型值为12KHz 17 //测的P1.0频率为11.7KHz 18 19 //所以CPU的实际MCLK大约为13.05/8=1.63KHz 20 */ 21 22 /* BCSCTL1 = CALBC1_1MHZ; // Set DCO 23 DCOCTL = CALDCO_1MHZ; 24 //ACLK 32.9KHz SMCLK 1.08MHz 与 980KHz 跳动 25 */ 26 27 /* BCSCTL1 = CALBC1_12MHZ; // Set DCO 28 DCOCTL = CALDCO_12MHZ; 29 //ACLK 32.9KHz SMCLK 12.4MHz 30 */ 31 32 33 BCSCTL1 = CALBC1_8MHZ; // Set DCO 34 DCOCTL = CALDCO_8MHZ; 35 //ACLK 32.9KHz SMCLK 7.6MHz 和 8.3MHz跳动 36 37 38 P1DIR = 0xFF; // All P1.x outputs 39 40 P1OUT = 0; // All P1.x reset 41 42 P2DIR = 0xFF; // All P2.x outputs 43 44 P2OUT = 0; // All P2.x reset 45 46 47 48 P1SEL |= BIT0+BIT4; // P10 P14options 功能选择为外围模块 49 50 //p10输出ACLK，来自VLO，p14输出SMCLK， 51 52 53 54 55 56 57 58 for (;;) 59 60 { 61 62 P1OUT |= 0x02; // P1.1 = 1 63 P1OUT &= ~0x02; // P1.1 = 0 64 65 } 66 67 68 }
使用固有DCO或者内部低频起振